This series adds fine grained trap control in EL2 required for FEAT_PMUv3p9 registers like PMICNTR_EL0, PMICFILTR_EL0, and PMUACR_EL1 which are already being used in the kernel. This is required to prevent their EL1 access trap into EL2.
The following commits that enabled access into FEAT_PMUv3p9 registers have already been merged upstream from 6.12 onwards.
d8226d8cfbaf ("perf: arm_pmuv3: Add support for Armv9.4 PMU instruction counter") 0bbff9ed8165 ("perf/arm_pmuv3: Add PMUv3.9 per counter EL0 access control")
The sysreg patches in this series are required for the final patch which fixes the actual problem.
Anshuman Khandual (7): arm64/sysreg: Update register fields for ID_AA64MMFR0_EL1 arm64/sysreg: Add register fields for HDFGRTR2_EL2 arm64/sysreg: Add register fields for HDFGWTR2_EL2 arm64/sysreg: Add register fields for HFGITR2_EL2 arm64/sysreg: Add register fields for HFGRTR2_EL2 arm64/sysreg: Add register fields for HFGWTR2_EL2 arm64/boot: Enable EL2 requirements for FEAT_PMUv3p9
Rob Herring (Arm) (1): perf/arm_pmuv3: Add PMUv3.9 per counter EL0 access control
Documentation/arch/arm64/booting.rst | 22 ++++++ arch/arm/include/asm/arm_pmuv3.h | 6 ++ arch/arm64/include/asm/arm_pmuv3.h | 10 +++ arch/arm64/include/asm/el2_setup.h | 25 ++++++ arch/arm64/tools/sysreg | 111 +++++++++++++++++++++++++++ drivers/perf/arm_pmuv3.c | 29 ++++--- include/linux/perf/arm_pmuv3.h | 1 + 7 files changed, 194 insertions(+), 10 deletions(-)
From: "Rob Herring (Arm)" robh@kernel.org
Armv8.9/9.4 PMUv3.9 adds per counter EL0 access controls. Per counter access is enabled with the UEN bit in PMUSERENR_EL1 register. Individual counters are enabled/disabled in the PMUACR_EL1 register. When UEN is set, the CR/ER bits control EL0 write access and must be set to disable write access.
With the access controls, the clearing of unused counters can be skipped.
KVM also configures PMUSERENR_EL1 in order to trap to EL2. UEN does not need to be set for it since only PMUv3.5 is exposed to guests.
Signed-off-by: Rob Herring (Arm) robh@kernel.org Link: https://lore.kernel.org/r/20241002184326.1105499-1-robh@kernel.org Signed-off-by: Will Deacon will@kernel.org [cherry picked from commit 0bbff9ed81654d5f06bfca484681756ee407f924] Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com --- arch/arm/include/asm/arm_pmuv3.h | 6 ++++++ arch/arm64/include/asm/arm_pmuv3.h | 10 ++++++++++ arch/arm64/tools/sysreg | 8 ++++++++ drivers/perf/arm_pmuv3.c | 29 +++++++++++++++++++---------- include/linux/perf/arm_pmuv3.h | 1 + 5 files changed, 44 insertions(+), 10 deletions(-)
diff --git a/arch/arm/include/asm/arm_pmuv3.h b/arch/arm/include/asm/arm_pmuv3.h index f63ba8986b24..d242b5e1ca0d 100644 --- a/arch/arm/include/asm/arm_pmuv3.h +++ b/arch/arm/include/asm/arm_pmuv3.h @@ -231,6 +231,7 @@ static inline void kvm_vcpu_pmu_resync_el0(void) {} #define ARMV8_PMU_DFR_VER_V3P1 0x4 #define ARMV8_PMU_DFR_VER_V3P4 0x5 #define ARMV8_PMU_DFR_VER_V3P5 0x6 +#define ARMV8_PMU_DFR_VER_V3P9 0x9 #define ARMV8_PMU_DFR_VER_IMP_DEF 0xF
static inline bool pmuv3_implemented(int pmuver) @@ -249,6 +250,11 @@ static inline bool is_pmuv3p5(int pmuver) return pmuver >= ARMV8_PMU_DFR_VER_V3P5; }
+static inline bool is_pmuv3p9(int pmuver) +{ + return pmuver >= ARMV8_PMU_DFR_VER_V3P9; +} + static inline u64 read_pmceid0(void) { u64 val = read_sysreg(PMCEID0); diff --git a/arch/arm64/include/asm/arm_pmuv3.h b/arch/arm64/include/asm/arm_pmuv3.h index 468a049bc63b..8a777dec8d88 100644 --- a/arch/arm64/include/asm/arm_pmuv3.h +++ b/arch/arm64/include/asm/arm_pmuv3.h @@ -152,6 +152,11 @@ static inline void write_pmuserenr(u32 val) write_sysreg(val, pmuserenr_el0); }
+static inline void write_pmuacr(u64 val) +{ + write_sysreg_s(val, SYS_PMUACR_EL1); +} + static inline u64 read_pmceid0(void) { return read_sysreg(pmceid0_el0); @@ -178,4 +183,9 @@ static inline bool is_pmuv3p5(int pmuver) return pmuver >= ID_AA64DFR0_EL1_PMUVer_V3P5; }
+static inline bool is_pmuv3p9(int pmuver) +{ + return pmuver >= ID_AA64DFR0_EL1_PMUVer_V3P9; +} + #endif diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 8d637ac4b7c6..74fb5af91d4f 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1238,6 +1238,7 @@ UnsignedEnum 11:8 PMUVer 0b0110 V3P5 0b0111 V3P7 0b1000 V3P8 + 0b1001 V3P9 0b1111 IMP_DEF EndEnum UnsignedEnum 7:4 TraceVer @@ -2178,6 +2179,13 @@ Field 4 P Field 3:0 ALIGN EndSysreg
+Sysreg PMUACR_EL1 3 0 9 14 4 +Res0 63:33 +Field 32 F0 +Field 31 C +Field 30:0 P +EndSysreg + Sysreg PMSELR_EL0 3 3 9 12 5 Res0 63:5 Field 4:0 SEL diff --git a/drivers/perf/arm_pmuv3.c b/drivers/perf/arm_pmuv3.c index 0afe02f879b4..bb93d32b86ea 100644 --- a/drivers/perf/arm_pmuv3.c +++ b/drivers/perf/arm_pmuv3.c @@ -770,18 +770,27 @@ static void armv8pmu_enable_user_access(struct arm_pmu *cpu_pmu) int i; struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events);
- /* Clear any unused counters to avoid leaking their contents */ - for_each_andnot_bit(i, cpu_pmu->cntr_mask, cpuc->used_mask, - ARMPMU_MAX_HWEVENTS) { - if (i == ARMV8_PMU_CYCLE_IDX) - write_pmccntr(0); - else if (i == ARMV8_PMU_INSTR_IDX) - write_pmicntr(0); - else - armv8pmu_write_evcntr(i, 0); + if (is_pmuv3p9(cpu_pmu->pmuver)) { + u64 mask = 0; + for_each_set_bit(i, cpuc->used_mask, ARMPMU_MAX_HWEVENTS) { + if (armv8pmu_event_has_user_read(cpuc->events[i])) + mask |= BIT(i); + } + write_pmuacr(mask); + } else { + /* Clear any unused counters to avoid leaking their contents */ + for_each_andnot_bit(i, cpu_pmu->cntr_mask, cpuc->used_mask, + ARMPMU_MAX_HWEVENTS) { + if (i == ARMV8_PMU_CYCLE_IDX) + write_pmccntr(0); + else if (i == ARMV8_PMU_INSTR_IDX) + write_pmicntr(0); + else + armv8pmu_write_evcntr(i, 0); + } }
- update_pmuserenr(ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_CR); + update_pmuserenr(ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_UEN); }
static void armv8pmu_enable_event(struct perf_event *event) diff --git a/include/linux/perf/arm_pmuv3.h b/include/linux/perf/arm_pmuv3.h index 3372c1b56486..d698efba28a2 100644 --- a/include/linux/perf/arm_pmuv3.h +++ b/include/linux/perf/arm_pmuv3.h @@ -257,6 +257,7 @@ #define ARMV8_PMU_USERENR_SW (1 << 1) /* PMSWINC can be written at EL0 */ #define ARMV8_PMU_USERENR_CR (1 << 2) /* Cycle counter can be read at EL0 */ #define ARMV8_PMU_USERENR_ER (1 << 3) /* Event counter can be read at EL0 */ +#define ARMV8_PMU_USERENR_UEN (1 << 4) /* Fine grained per counter access at EL0 */ /* Mask for writable bits */ #define ARMV8_PMU_USERENR_MASK (ARMV8_PMU_USERENR_EN | ARMV8_PMU_USERENR_SW | \ ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_ER)
[ Sasha's backport helper bot ]
Hi,
Summary of potential issues: ❌ Build failures detected ⚠️ Found matching upstream commit but patch is missing proper reference to it ⚠️ Found follow-up fixes in mainline
Found matching upstream commit: 0bbff9ed81654d5f06bfca484681756ee407f924
WARNING: Author mismatch between patch and found commit: Backport author: Anshuman Khandualanshuman.khandual@arm.com Commit author: Rob Herring (Arm)robh@kernel.org
Status in newer kernel trees: 6.14.y | Present (exact SHA1) 6.13.y | Present (exact SHA1)
Found fixes commits: 858c7bfcb35e arm64/boot: Enable EL2 requirements for FEAT_PMUv3p9 bdc9a64c8b20 ARM: pmuv3: Add missing write_pmuacr()
Note: The patch differs from the upstream commit: --- 1: 0bbff9ed81654 ! 1: 876f9c2d718e5 perf/arm_pmuv3: Add PMUv3.9 per counter EL0 access control @@ Commit message Signed-off-by: Rob Herring (Arm) robh@kernel.org Link: https://lore.kernel.org/r/20241002184326.1105499-1-robh@kernel.org Signed-off-by: Will Deacon will@kernel.org + [cherry picked from commit 0bbff9ed81654d5f06bfca484681756ee407f924] + Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com
## arch/arm/include/asm/arm_pmuv3.h ## @@ arch/arm/include/asm/arm_pmuv3.h: static inline void kvm_vcpu_pmu_resync_el0(void) {} ---
Results of testing on various branches:
| Branch | Patch Apply | Build Test | |---------------------------|-------------|------------| | stable/linux-6.12.y | Success | Failed |
Build Errors: Build error: during RTL pass: bbro drivers/gpu/drm/amd/amdgpu/../display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c: In function 'dml_core_mode_support': drivers/gpu/drm/amd/amdgpu/../display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c:9211:1: internal compiler error: in df_compact_blocks, at df-core.cc:1746 9211 | } | ^ 0x7f8f45e06d67 __libc_start_call_main ../sysdeps/nptl/libc_start_call_main.h:58 0x7f8f45e06e24 __libc_start_main_impl ../csu/libc-start.c:360 Please submit a full bug report, with preprocessed source (by using -freport-bug). Please include the complete backtrace with any bug report. See https://gcc.gnu.org/bugs/ for instructions. make[6]: *** [scripts/Makefile.build:229: drivers/gpu/drm/amd/amdgpu/../display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.o] Error 1 make[6]: Target 'drivers/gpu/drm/amd/amdgpu/' not remade because of errors. make[5]: *** [scripts/Makefile.build:478: drivers/gpu/drm/amd/amdgpu] Error 2 make[5]: Target 'drivers/gpu/drm/' not remade because of errors. make[4]: *** [scripts/Makefile.build:478: drivers/gpu/drm] Error 2 make[4]: Target 'drivers/gpu/' not remade because of errors. make[3]: *** [scripts/Makefile.build:478: drivers/gpu] Error 2 make[3]: Target 'drivers/' not remade because of errors. make[2]: *** [scripts/Makefile.build:478: drivers] Error 2 make[2]: Target './' not remade because of errors. make[1]: *** [/home/sasha/build/linus-next/Makefile:1944: .] Error 2 make[1]: Target '__all' not remade because of errors. make: *** [Makefile:224: __sub-make] Error 2 make: Target '__all' not remade because of errors.
On Wed, Apr 9, 2025 at 10:55 PM Anshuman Khandual anshuman.khandual@arm.com wrote:
From: "Rob Herring (Arm)" robh@kernel.org
Armv8.9/9.4 PMUv3.9 adds per counter EL0 access controls. Per counter access is enabled with the UEN bit in PMUSERENR_EL1 register. Individual counters are enabled/disabled in the PMUACR_EL1 register. When UEN is set, the CR/ER bits control EL0 write access and must be set to disable write access.
With the access controls, the clearing of unused counters can be skipped.
KVM also configures PMUSERENR_EL1 in order to trap to EL2. UEN does not need to be set for it since only PMUv3.5 is exposed to guests.
Signed-off-by: Rob Herring (Arm) robh@kernel.org Link: https://lore.kernel.org/r/20241002184326.1105499-1-robh@kernel.org Signed-off-by: Will Deacon will@kernel.org [cherry picked from commit 0bbff9ed81654d5f06bfca484681756ee407f924] Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com
This one doesn't belong in 6.12. It's a feature that landed in 6.13. It's only the fixed instruction counter support that landed in 6.12.
Rob
On 4/10/25 22:20, Rob Herring wrote:
On Wed, Apr 9, 2025 at 10:55 PM Anshuman Khandual anshuman.khandual@arm.com wrote:
From: "Rob Herring (Arm)" robh@kernel.org
Armv8.9/9.4 PMUv3.9 adds per counter EL0 access controls. Per counter access is enabled with the UEN bit in PMUSERENR_EL1 register. Individual counters are enabled/disabled in the PMUACR_EL1 register. When UEN is set, the CR/ER bits control EL0 write access and must be set to disable write access.
With the access controls, the clearing of unused counters can be skipped.
KVM also configures PMUSERENR_EL1 in order to trap to EL2. UEN does not need to be set for it since only PMUv3.5 is exposed to guests.
Signed-off-by: Rob Herring (Arm) robh@kernel.org Link: https://lore.kernel.org/r/20241002184326.1105499-1-robh@kernel.org Signed-off-by: Will Deacon will@kernel.org [cherry picked from commit 0bbff9ed81654d5f06bfca484681756ee407f924] Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com
This one doesn't belong in 6.12. It's a feature that landed in 6.13. It's only the fixed instruction counter support that landed in 6.12.
Are you suggesting that this patch is not required for 6.12.y backport ? We need this commit for ID_AA64DFR0_EL1_PMUVer_V3P9 definition. Should this change be added in the last commit itself in the series instead ?
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 8d637ac4b7c6..74fb5af91d4f 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1238,6 +1238,7 @@ UnsignedEnum 11:8 PMUVer 0b0110 V3P5 0b0111 V3P7 0b1000 V3P8 + 0b1001 V3P9 0b1111 IMP_DEF EndEnum UnsignedEnum 7:4 TraceVer @@ -2178,6 +2179,13 @@ Field 4 P Field 3:0 ALIGN EndSysreg
On Thu, Apr 10, 2025 at 11:24 PM Anshuman Khandual anshuman.khandual@arm.com wrote:
On 4/10/25 22:20, Rob Herring wrote:
On Wed, Apr 9, 2025 at 10:55 PM Anshuman Khandual anshuman.khandual@arm.com wrote:
From: "Rob Herring (Arm)" robh@kernel.org
Armv8.9/9.4 PMUv3.9 adds per counter EL0 access controls. Per counter access is enabled with the UEN bit in PMUSERENR_EL1 register. Individual counters are enabled/disabled in the PMUACR_EL1 register. When UEN is set, the CR/ER bits control EL0 write access and must be set to disable write access.
With the access controls, the clearing of unused counters can be skipped.
KVM also configures PMUSERENR_EL1 in order to trap to EL2. UEN does not need to be set for it since only PMUv3.5 is exposed to guests.
Signed-off-by: Rob Herring (Arm) robh@kernel.org Link: https://lore.kernel.org/r/20241002184326.1105499-1-robh@kernel.org Signed-off-by: Will Deacon will@kernel.org [cherry picked from commit 0bbff9ed81654d5f06bfca484681756ee407f924] Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com
This one doesn't belong in 6.12. It's a feature that landed in 6.13. It's only the fixed instruction counter support that landed in 6.12.
Are you suggesting that this patch is not required for 6.12.y backport ?
Yes.
We need this commit for ID_AA64DFR0_EL1_PMUVer_V3P9 definition. Should this change be added in the last commit itself in the series instead ?
Ah, that's unfortunate. I suppose adding the hunk to the last commit is the easiest. Not sure what the preference would be here.
Rob
On Fri, Apr 11, 2025 at 8:03 AM Rob Herring robh@kernel.org wrote:
On Thu, Apr 10, 2025 at 11:24 PM Anshuman Khandual anshuman.khandual@arm.com wrote:
On 4/10/25 22:20, Rob Herring wrote:
On Wed, Apr 9, 2025 at 10:55 PM Anshuman Khandual anshuman.khandual@arm.com wrote:
From: "Rob Herring (Arm)" robh@kernel.org
Armv8.9/9.4 PMUv3.9 adds per counter EL0 access controls. Per counter access is enabled with the UEN bit in PMUSERENR_EL1 register. Individual counters are enabled/disabled in the PMUACR_EL1 register. When UEN is set, the CR/ER bits control EL0 write access and must be set to disable write access.
With the access controls, the clearing of unused counters can be skipped.
KVM also configures PMUSERENR_EL1 in order to trap to EL2. UEN does not need to be set for it since only PMUv3.5 is exposed to guests.
Signed-off-by: Rob Herring (Arm) robh@kernel.org Link: https://lore.kernel.org/r/20241002184326.1105499-1-robh@kernel.org Signed-off-by: Will Deacon will@kernel.org [cherry picked from commit 0bbff9ed81654d5f06bfca484681756ee407f924] Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com
This one doesn't belong in 6.12. It's a feature that landed in 6.13. It's only the fixed instruction counter support that landed in 6.12.
Are you suggesting that this patch is not required for 6.12.y backport ?
Yes.
We need this commit for ID_AA64DFR0_EL1_PMUVer_V3P9 definition. Should this change be added in the last commit itself in the series instead ?
Ah, that's unfortunate. I suppose adding the hunk to the last commit is the easiest. Not sure what the preference would be here.
You could also change the comparison from <3.9 to <=3.8 and avoid needing the definition.
Rob
On 4/11/25 18:35, Rob Herring wrote:
On Fri, Apr 11, 2025 at 8:03 AM Rob Herring robh@kernel.org wrote:
On Thu, Apr 10, 2025 at 11:24 PM Anshuman Khandual anshuman.khandual@arm.com wrote:
On 4/10/25 22:20, Rob Herring wrote:
On Wed, Apr 9, 2025 at 10:55 PM Anshuman Khandual anshuman.khandual@arm.com wrote:
From: "Rob Herring (Arm)" robh@kernel.org
Armv8.9/9.4 PMUv3.9 adds per counter EL0 access controls. Per counter access is enabled with the UEN bit in PMUSERENR_EL1 register. Individual counters are enabled/disabled in the PMUACR_EL1 register. When UEN is set, the CR/ER bits control EL0 write access and must be set to disable write access.
With the access controls, the clearing of unused counters can be skipped.
KVM also configures PMUSERENR_EL1 in order to trap to EL2. UEN does not need to be set for it since only PMUv3.5 is exposed to guests.
Signed-off-by: Rob Herring (Arm) robh@kernel.org Link: https://lore.kernel.org/r/20241002184326.1105499-1-robh@kernel.org Signed-off-by: Will Deacon will@kernel.org [cherry picked from commit 0bbff9ed81654d5f06bfca484681756ee407f924] Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com
This one doesn't belong in 6.12. It's a feature that landed in 6.13. It's only the fixed instruction counter support that landed in 6.12.
Are you suggesting that this patch is not required for 6.12.y backport ?
Yes.
We need this commit for ID_AA64DFR0_EL1_PMUVer_V3P9 definition. Should this change be added in the last commit itself in the series instead ?
Ah, that's unfortunate. I suppose adding the hunk to the last commit is the easiest. Not sure what the preference would be here.
You could also change the comparison from <3.9 to <=3.8 and avoid needing the definition.
.macro __init_el2_fgt2 .............. .............. cmp x1, #ID_AA64DFR0_EL1_PMUVer_V3P9 <========= b.lt .Lskip_pmuv3p9_@
orr x0, x0, #HDFGRTR2_EL2_nPMICNTR_EL0 orr x0, x0, #HDFGRTR2_EL2_nPMICFILTR_EL0 orr x0, x0, #HDFGRTR2_EL2_nPMUACR_EL1
Are you suggesting that the above check against ID_AA64DFR0_EL1_PMUVer_V3P9 be replaced with ID_AA64DFR0_EL1_PMUVer_V3P8 instead ? But EL3 trap disable for PMUACR_EL1 is only applicable when FEAT_PMUv3p9 is enabled.
Also seems like adding a hunk defining ID_AA64DFR0_EL1_PMUVer_V3P9 is much cleaner and easier to follow rather than changing the comparison here IMHO.
But will be happy to change as preferred.
This updates ID_AA64MMFR0_EL1 register fields as per the definitions based on DDI0601 2024-12.
Cc: Will Deacon will@kernel.org Cc: Mark Brown broonie@kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Eric Auger eric.auger@redhat.com Reviewed-by: Mark Brown broonie@kernel.org Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com Link: https://lore.kernel.org/r/20250203050828.1049370-2-anshuman.khandual@arm.com Signed-off-by: Catalin Marinas catalin.marinas@arm.com [cherry picked from commit cc15f548cc77574bcd68425ae01a796659bd3705] Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com --- arch/arm64/tools/sysreg | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 74fb5af91d4f..dd33cbaebad5 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1557,6 +1557,7 @@ EndEnum UnsignedEnum 59:56 FGT 0b0000 NI 0b0001 IMP + 0b0010 FGT2 EndEnum Res0 55:48 UnsignedEnum 47:44 EXS @@ -1618,6 +1619,7 @@ Enum 3:0 PARANGE 0b0100 44 0b0101 48 0b0110 52 + 0b0111 56 EndEnum EndSysreg
This adds register fields for HDFGRTR2_EL2 as per the definitions based on DDI0601 2024-12.
Cc: Will Deacon will@kernel.org Cc: Mark Brown broonie@kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Eric Auger eric.auger@redhat.com Reviewed-by: Mark Brown broonie@kernel.org Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com Link: https://lore.kernel.org/r/20250203050828.1049370-3-anshuman.khandual@arm.com Signed-off-by: Catalin Marinas catalin.marinas@arm.com [cherry picked from commit 44844551670cff70a8aa5c1cde27ad1e0367e009] Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com --- arch/arm64/tools/sysreg | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index dd33cbaebad5..56dfdca0ce10 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2473,6 +2473,35 @@ Field 1 ICIALLU Field 0 ICIALLUIS EndSysreg
+Sysreg HDFGRTR2_EL2 3 4 3 1 0 +Res0 63:25 +Field 24 nPMBMAR_EL1 +Field 23 nMDSTEPOP_EL1 +Field 22 nTRBMPAM_EL1 +Res0 21 +Field 20 nTRCITECR_EL1 +Field 19 nPMSDSFR_EL1 +Field 18 nSPMDEVAFF_EL1 +Field 17 nSPMID +Field 16 nSPMSCR_EL1 +Field 15 nSPMACCESSR_EL1 +Field 14 nSPMCR_EL0 +Field 13 nSPMOVS +Field 12 nSPMINTEN +Field 11 nSPMCNTEN +Field 10 nSPMSELR_EL0 +Field 9 nSPMEVTYPERn_EL0 +Field 8 nSPMEVCNTRn_EL0 +Field 7 nPMSSCR_EL1 +Field 6 nPMSSDATA +Field 5 nMDSELR_EL1 +Field 4 nPMUACR_EL1 +Field 3 nPMICFILTR_EL0 +Field 2 nPMICNTR_EL0 +Field 1 nPMIAR_EL1 +Field 0 nPMECR_EL1 +EndSysreg + Sysreg HDFGRTR_EL2 3 4 3 1 4 Field 63 PMBIDR_EL1 Field 62 nPMSNEVFR_EL1
This adds register fields for HDFGWTR2_EL2 as per the definitions based on DDI0601 2024-12.
Cc: Will Deacon will@kernel.org Cc: Mark Brown broonie@kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Eric Auger eric.auger@redhat.com Reviewed-by: Mark Brown broonie@kernel.org Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com Link: https://lore.kernel.org/r/20250203050828.1049370-4-anshuman.khandual@arm.com Signed-off-by: Catalin Marinas catalin.marinas@arm.com [cherry picked from commit 2f1f62a1257b9d5eb98a8e161ea7d11f1678f7ad] Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com --- arch/arm64/tools/sysreg | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 56dfdca0ce10..dfa388e6b6de 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2502,6 +2502,34 @@ Field 1 nPMIAR_EL1 Field 0 nPMECR_EL1 EndSysreg
+Sysreg HDFGWTR2_EL2 3 4 3 1 1 +Res0 63:25 +Field 24 nPMBMAR_EL1 +Field 23 nMDSTEPOP_EL1 +Field 22 nTRBMPAM_EL1 +Field 21 nPMZR_EL0 +Field 20 nTRCITECR_EL1 +Field 19 nPMSDSFR_EL1 +Res0 18:17 +Field 16 nSPMSCR_EL1 +Field 15 nSPMACCESSR_EL1 +Field 14 nSPMCR_EL0 +Field 13 nSPMOVS +Field 12 nSPMINTEN +Field 11 nSPMCNTEN +Field 10 nSPMSELR_EL0 +Field 9 nSPMEVTYPERn_EL0 +Field 8 nSPMEVCNTRn_EL0 +Field 7 nPMSSCR_EL1 +Res0 6 +Field 5 nMDSELR_EL1 +Field 4 nPMUACR_EL1 +Field 3 nPMICFILTR_EL0 +Field 2 nPMICNTR_EL0 +Field 1 nPMIAR_EL1 +Field 0 nPMECR_EL1 +EndSysreg + Sysreg HDFGRTR_EL2 3 4 3 1 4 Field 63 PMBIDR_EL1 Field 62 nPMSNEVFR_EL1
This adds register fields for HFGITR2_EL2 as per the definitions based on DDI0601 2024-12.
Cc: Will Deacon will@kernel.org Cc: Mark Brown broonie@kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Eric Auger eric.auger@redhat.com Reviewed-by: Mark Brown broonie@kernel.org Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com Link: https://lore.kernel.org/r/20250203050828.1049370-5-anshuman.khandual@arm.com Signed-off-by: Catalin Marinas catalin.marinas@arm.com [cherry picked from commit 9401476f17747586a8bfb29abfdf5ade7a8bceef] Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com --- arch/arm64/tools/sysreg | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index dfa388e6b6de..6e29235e0f44 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2702,6 +2702,12 @@ Field 1 AMEVCNTR00_EL0 Field 0 AMCNTEN0 EndSysreg
+Sysreg HFGITR2_EL2 3 4 3 1 7 +Res0 63:2 +Field 1 nDCCIVAPS +Field 0 TSBCSYNC +EndSysreg + Sysreg ZCR_EL2 3 4 1 2 0 Fields ZCR_ELx EndSysreg
This adds register fields for HFGRTR2_EL2 as per the definitions based on DDI0601 2024-12.
Cc: Will Deacon will@kernel.org Cc: Mark Brown broonie@kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Eric Auger eric.auger@redhat.com Reviewed-by: Mark Brown broonie@kernel.org Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com Link: https://lore.kernel.org/r/20250203050828.1049370-6-anshuman.khandual@arm.com Signed-off-by: Catalin Marinas catalin.marinas@arm.com [cherry picked from commit 59236089ad5243377b6905d78e39ba4183dc35f5] Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com --- arch/arm64/tools/sysreg | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 6e29235e0f44..2c0f6d7ba386 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2530,6 +2530,25 @@ Field 1 nPMIAR_EL1 Field 0 nPMECR_EL1 EndSysreg
+Sysreg HFGRTR2_EL2 3 4 3 1 2 +Res0 63:15 +Field 14 nACTLRALIAS_EL1 +Field 13 nACTLRMASK_EL1 +Field 12 nTCR2ALIAS_EL1 +Field 11 nTCRALIAS_EL1 +Field 10 nSCTLRALIAS2_EL1 +Field 9 nSCTLRALIAS_EL1 +Field 8 nCPACRALIAS_EL1 +Field 7 nTCR2MASK_EL1 +Field 6 nTCRMASK_EL1 +Field 5 nSCTLR2MASK_EL1 +Field 4 nSCTLRMASK_EL1 +Field 3 nCPACRMASK_EL1 +Field 2 nRCWSMASK_EL1 +Field 1 nERXGSR_EL1 +Field 0 nPFAR_EL1 +EndSysreg + Sysreg HDFGRTR_EL2 3 4 3 1 4 Field 63 PMBIDR_EL1 Field 62 nPMSNEVFR_EL1
This adds register fields for HFGWTR2_EL2 as per the definitions based on DDI0601 2024-12.
Cc: Will Deacon will@kernel.org Cc: Mark Brown broonie@kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Eric Auger eric.auger@redhat.com Reviewed-by: Mark Brown broonie@kernel.org Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com Link: https://lore.kernel.org/r/20250203050828.1049370-7-anshuman.khandual@arm.com Signed-off-by: Catalin Marinas catalin.marinas@arm.com [cherry picked from commit ea37be0773f04420515b8db49e50abedbaa97e23] Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com --- arch/arm64/tools/sysreg | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 2c0f6d7ba386..1a12f56ab302 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2549,6 +2549,25 @@ Field 1 nERXGSR_EL1 Field 0 nPFAR_EL1 EndSysreg
+Sysreg HFGWTR2_EL2 3 4 3 1 3 +Res0 63:15 +Field 14 nACTLRALIAS_EL1 +Field 13 nACTLRMASK_EL1 +Field 12 nTCR2ALIAS_EL1 +Field 11 nTCRALIAS_EL1 +Field 10 nSCTLRALIAS2_EL1 +Field 9 nSCTLRALIAS_EL1 +Field 8 nCPACRALIAS_EL1 +Field 7 nTCR2MASK_EL1 +Field 6 nTCRMASK_EL1 +Field 5 nSCTLR2MASK_EL1 +Field 4 nSCTLRMASK_EL1 +Field 3 nCPACRMASK_EL1 +Field 2 nRCWSMASK_EL1 +Res0 1 +Field 0 nPFAR_EL1 +EndSysreg + Sysreg HDFGRTR_EL2 3 4 3 1 4 Field 63 PMBIDR_EL1 Field 62 nPMSNEVFR_EL1
FEAT_PMUv3p9 registers such as PMICNTR_EL0, PMICFILTR_EL0, and PMUACR_EL1 access from EL1 requires appropriate EL2 fine grained trap configuration via FEAT_FGT2 based trap control registers HDFGRTR2_EL2 and HDFGWTR2_EL2. Otherwise such register accesses will result in traps into EL2.
Add a new helper __init_el2_fgt2() which initializes FEAT_FGT2 based fine grained trap control registers HDFGRTR2_EL2 and HDFGWTR2_EL2 (setting the bits nPMICNTR_EL0, nPMICFILTR_EL0 and nPMUACR_EL1) to enable access into PMICNTR_EL0, PMICFILTR_EL0, and PMUACR_EL1 registers.
Also update booting.rst with SCR_EL3.FGTEn2 requirement for all FEAT_FGT2 based registers to be accessible in EL2.
Cc: Will Deacon will@kernel.org Cc: Mark Rutland mark.rutland@arm.com Cc: Rob Herring robh@kernel.org Cc: Jonathan Corbet corbet@lwn.net Cc: Marc Zyngier maz@kernel.org Cc: Oliver Upton oliver.upton@linux.dev Cc: linux-arm-kernel@lists.infradead.org Cc: linux-doc@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: kvmarm@lists.linux.dev Fixes: 0bbff9ed8165 ("perf/arm_pmuv3: Add PMUv3.9 per counter EL0 access control") Fixes: d8226d8cfbaf ("perf: arm_pmuv3: Add support for Armv9.4 PMU instruction counter") Tested-by: Rob Herring (Arm) robh@kernel.org Reviewed-by: Rob Herring (Arm) robh@kernel.org Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com Link: https://lore.kernel.org/r/20250227035119.2025171-1-anshuman.khandual@arm.com Signed-off-by: Catalin Marinas catalin.marinas@arm.com [cherry picked from commit 858c7bfcb35e1100b58bb63c9f562d86e09418d9] Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com --- Documentation/arch/arm64/booting.rst | 22 ++++++++++++++++++++++ arch/arm64/include/asm/el2_setup.h | 25 +++++++++++++++++++++++++ 2 files changed, 47 insertions(+)
diff --git a/Documentation/arch/arm64/booting.rst b/Documentation/arch/arm64/booting.rst index b57776a68f15..15bcd1b4003a 100644 --- a/Documentation/arch/arm64/booting.rst +++ b/Documentation/arch/arm64/booting.rst @@ -285,6 +285,12 @@ Before jumping into the kernel, the following conditions must be met:
- SCR_EL3.FGTEn (bit 27) must be initialised to 0b1.
+ For CPUs with the Fine Grained Traps 2 (FEAT_FGT2) extension present: + + - If EL3 is present and the kernel is entered at EL2: + + - SCR_EL3.FGTEn2 (bit 59) must be initialised to 0b1. + For CPUs with support for HCRX_EL2 (FEAT_HCX) present:
- If EL3 is present and the kernel is entered at EL2: @@ -379,6 +385,22 @@ Before jumping into the kernel, the following conditions must be met:
- SMCR_EL2.EZT0 (bit 30) must be initialised to 0b1.
+ For CPUs with the Performance Monitors Extension (FEAT_PMUv3p9): + + - If EL3 is present: + + - MDCR_EL3.EnPM2 (bit 7) must be initialised to 0b1. + + - If the kernel is entered at EL1 and EL2 is present: + + - HDFGRTR2_EL2.nPMICNTR_EL0 (bit 2) must be initialised to 0b1. + - HDFGRTR2_EL2.nPMICFILTR_EL0 (bit 3) must be initialised to 0b1. + - HDFGRTR2_EL2.nPMUACR_EL1 (bit 4) must be initialised to 0b1. + + - HDFGWTR2_EL2.nPMICNTR_EL0 (bit 2) must be initialised to 0b1. + - HDFGWTR2_EL2.nPMICFILTR_EL0 (bit 3) must be initialised to 0b1. + - HDFGWTR2_EL2.nPMUACR_EL1 (bit 4) must be initialised to 0b1. + For CPUs with Memory Copy and Memory Set instructions (FEAT_MOPS):
- If the kernel is entered at EL1 and EL2 is present: diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h index e0ffdf13a18b..bdbe9e08664a 100644 --- a/arch/arm64/include/asm/el2_setup.h +++ b/arch/arm64/include/asm/el2_setup.h @@ -215,6 +215,30 @@ .Lskip_fgt_@: .endm
+.macro __init_el2_fgt2 + mrs x1, id_aa64mmfr0_el1 + ubfx x1, x1, #ID_AA64MMFR0_EL1_FGT_SHIFT, #4 + cmp x1, #ID_AA64MMFR0_EL1_FGT_FGT2 + b.lt .Lskip_fgt2_@ + + mov x0, xzr + mrs x1, id_aa64dfr0_el1 + ubfx x1, x1, #ID_AA64DFR0_EL1_PMUVer_SHIFT, #4 + cmp x1, #ID_AA64DFR0_EL1_PMUVer_V3P9 + b.lt .Lskip_pmuv3p9_@ + + orr x0, x0, #HDFGRTR2_EL2_nPMICNTR_EL0 + orr x0, x0, #HDFGRTR2_EL2_nPMICFILTR_EL0 + orr x0, x0, #HDFGRTR2_EL2_nPMUACR_EL1 +.Lskip_pmuv3p9_@: + msr_s SYS_HDFGRTR2_EL2, x0 + msr_s SYS_HDFGWTR2_EL2, x0 + msr_s SYS_HFGRTR2_EL2, xzr + msr_s SYS_HFGWTR2_EL2, xzr + msr_s SYS_HFGITR2_EL2, xzr +.Lskip_fgt2_@: +.endm + .macro __init_el2_nvhe_prepare_eret mov x0, #INIT_PSTATE_EL1 msr spsr_el2, x0 @@ -240,6 +264,7 @@ __init_el2_nvhe_idregs __init_el2_cptr __init_el2_fgt + __init_el2_fgt2 .endm
#ifndef __KVM_NVHE_HYPERVISOR__
linux-stable-mirror@lists.linaro.org
-
Anshuman Khandual -
Rob Herring -
Sasha Levin