From: Xi Ruoyao xry111@xry111.site
commit f24f669d03f884a6ef95cca84317d0f329e93961 upstream.
Per the "Processor Specification Update" documentations referred by the intel-microcode-20240312 release note, this microcode release has fixed the issue for all affected models.
So don't disable PCID if the microcode is new enough. The precise minimum microcode revision fixing the issue was provided by Pawan Intel.
[ dhansen: comment and changelog tweaks ] [ pawan: backported to 6.1 s/ATOM_GRACEMONT/ALDERLAKE_N/ ]
Signed-off-by: Xi Ruoyao xry111@xry111.site Signed-off-by: Dave Hansen dave.hansen@linux.intel.com Acked-by: Pawan Gupta pawan.kumar.gupta@linux.intel.com Signed-off-by: Pawan Gupta pawan.kumar.gupta@linux.intel.com Link: https://lore.kernel.org/all/168436059559.404.13934972543631851306.tip-bot2@t... Link: https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/releases... Link: https://cdrdv2.intel.com/v1/dl/getContent/740518 # RPL042, rev. 13 Link: https://cdrdv2.intel.com/v1/dl/getContent/682436 # ADL063, rev. 24 Link: https://lore.kernel.org/all/20240325231300.qrltbzf6twm43ftb@desk/ Link: https://lore.kernel.org/all/20240522020625.69418-1-xry111%40xry111.site --- arch/x86/mm/init.c | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-)
diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c index ed861ef33f80..ab697ee64528 100644 --- a/arch/x86/mm/init.c +++ b/arch/x86/mm/init.c @@ -263,28 +263,33 @@ static void __init probe_page_size_mask(void) }
/* - * INVLPG may not properly flush Global entries - * on these CPUs when PCIDs are enabled. + * INVLPG may not properly flush Global entries on + * these CPUs. New microcode fixes the issue. */ static const struct x86_cpu_id invlpg_miss_ids[] = { - X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE, 0), - X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, 0), - X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_N, 0), - X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE, 0), - X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P, 0), - X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_S, 0), + X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE, 0x2e), + X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, 0x42c), + X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_N, 0x11), + X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE, 0x118), + X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P, 0x4117), + X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_S, 0x2e), {} };
static void setup_pcid(void) { + const struct x86_cpu_id *invlpg_miss_match; + if (!IS_ENABLED(CONFIG_X86_64)) return;
if (!boot_cpu_has(X86_FEATURE_PCID)) return;
- if (x86_match_cpu(invlpg_miss_ids)) { + invlpg_miss_match = x86_match_cpu(invlpg_miss_ids); + + if (invlpg_miss_match && + boot_cpu_data.microcode < invlpg_miss_match->driver_data) { pr_info("Incomplete global flushes, disabling PCID"); setup_clear_cpu_cap(X86_FEATURE_PCID); return;
--- base-commit: 6ae7ac5c4251b139da4b672fe4157f2089a9d922 change-id: 20250307-clear-pcid-6-1-3f7b1af35cb2
Best regards,
[ Sasha's backport helper bot ]
Hi,
✅ All tests passed successfully. No issues detected. No action required from the submitter.
The upstream commit SHA1 provided is correct: f24f669d03f884a6ef95cca84317d0f329e93961
WARNING: Author mismatch between patch and upstream commit: Backport author: Pawan Guptapawan.kumar.gupta@linux.intel.com Commit author: Xi Ruoyaoxry111@xry111.site
Status in newer kernel trees: 6.13.y | Present (exact SHA1) 6.12.y | Not found 6.6.y | Not found
Note: The patch differs from the upstream commit: --- 1: f24f669d03f88 ! 1: 52d35a0a69a69 x86/mm: Don't disable PCID when INVLPG has been fixed by microcode @@ Metadata ## Commit message ## x86/mm: Don't disable PCID when INVLPG has been fixed by microcode
+ commit f24f669d03f884a6ef95cca84317d0f329e93961 upstream. + Per the "Processor Specification Update" documentations referred by the intel-microcode-20240312 release note, this microcode release has fixed the issue for all affected models. @@ Commit message Intel.
[ dhansen: comment and changelog tweaks ] + [ pawan: backported to 6.1 + s/ATOM_GRACEMONT/ALDERLAKE_N/ ]
Signed-off-by: Xi Ruoyao xry111@xry111.site Signed-off-by: Dave Hansen dave.hansen@linux.intel.com Acked-by: Pawan Gupta pawan.kumar.gupta@linux.intel.com + Signed-off-by: Pawan Gupta pawan.kumar.gupta@linux.intel.com Link: https://lore.kernel.org/all/168436059559.404.13934972543631851306.tip-bot2@t... Link: https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/releases... Link: https://cdrdv2.intel.com/v1/dl/getContent/740518 # RPL042, rev. 13 @@ arch/x86/mm/init.c: static void __init probe_page_size_mask(void) + * these CPUs. New microcode fixes the issue. */ static const struct x86_cpu_id invlpg_miss_ids[] = { -- X86_MATCH_VFM(INTEL_ALDERLAKE, 0), -- X86_MATCH_VFM(INTEL_ALDERLAKE_L, 0), -- X86_MATCH_VFM(INTEL_ATOM_GRACEMONT, 0), -- X86_MATCH_VFM(INTEL_RAPTORLAKE, 0), -- X86_MATCH_VFM(INTEL_RAPTORLAKE_P, 0), -- X86_MATCH_VFM(INTEL_RAPTORLAKE_S, 0), -+ X86_MATCH_VFM(INTEL_ALDERLAKE, 0x2e), -+ X86_MATCH_VFM(INTEL_ALDERLAKE_L, 0x42c), -+ X86_MATCH_VFM(INTEL_ATOM_GRACEMONT, 0x11), -+ X86_MATCH_VFM(INTEL_RAPTORLAKE, 0x118), -+ X86_MATCH_VFM(INTEL_RAPTORLAKE_P, 0x4117), -+ X86_MATCH_VFM(INTEL_RAPTORLAKE_S, 0x2e), +- X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE, 0), +- X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, 0), +- X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_N, 0), +- X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE, 0), +- X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P, 0), +- X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_S, 0), ++ X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE, 0x2e), ++ X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, 0x42c), ++ X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_N, 0x11), ++ X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE, 0x118), ++ X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P, 0x4117), ++ X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_S, 0x2e), {} };
---
Results of testing on various branches:
| Branch | Patch Apply | Build Test | |---------------------------|-------------|------------| | stable/linux-6.1.y | Success | Success |
linux-stable-mirror@lists.linaro.org
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Pawan Gupta -
Sasha Levin