Pentium 4's which are INTEL_P4_PRESCOTT (model 0x03) and later have a constant TSC. This was correctly captured until commit fadb6f569b10 ("x86/cpu/intel: Limit the non-architectural constant_tsc model checks"). In that commit, an error was introduced while selecting the last P4 model (0x06) as the upper bound. Model 0x06 was transposed to INTEL_P4_WILLAMETTE, which is just plain wrong. That was presumably a simple typo, probably just copying and pasting the wrong P4 model. Fix the constant TSC logic to cover all later P4 models. End at INTEL_P4_CEDARMILL which accurately corresponds to the last P4 model. Fixes: fadb6f569b10 ("x86/cpu/intel: Limit the non-architectural constant_tsc model checks")
Cc: stable@vger.kernel.org # v6.15
Signed-off-by: Suchit Karunakaran suchitkarunakaran@gmail.com
Changes since v3: - Refined changelog
Changes since v2: - Improve commit message
Changes since v1: - Fix incorrect logic
--- arch/x86/kernel/cpu/intel.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 076eaa41b8c8..6f5bd5dbc249 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -262,7 +262,7 @@ static void early_init_intel(struct cpuinfo_x86 *c) if (c->x86_power & (1 << 8)) { set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); - } else if ((c->x86_vfm >= INTEL_P4_PRESCOTT && c->x86_vfm <= INTEL_P4_WILLAMETTE) || + } else if ((c->x86_vfm >= INTEL_P4_PRESCOTT && c->x86_vfm <= INTEL_P4_CEDARMILL) || (c->x86_vfm >= INTEL_CORE_YONAH && c->x86_vfm <= INTEL_IVYBRIDGE)) { set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); }
Hi Suchit
I would strongly suggest spending more time understanding reviewer feedback and incorporating it before sending another version. Most of the comments below are a repeat from previous reviews by multiple folks.
On 8/4/2025 10:59 AM, Suchit Karunakaran wrote:
Pentium 4's which are INTEL_P4_PRESCOTT (model 0x03) and later have a constant TSC. This was correctly captured until commit fadb6f569b10 ("x86/cpu/intel: Limit the non-architectural constant_tsc model checks"). In that commit, an error was introduced while selecting the last P4 model (0x06) as the upper bound. Model 0x06 was transposed to INTEL_P4_WILLAMETTE, which is just plain wrong. That was presumably a simple typo, probably just copying and pasting the wrong P4 model. Fix the constant TSC logic to cover all later P4 models. End at INTEL_P4_CEDARMILL which accurately corresponds to the last P4 model.
Please use proper spacing and line breaks. Posting this as a single chunk makes it very hard to read.
Fixes: fadb6f569b10 ("x86/cpu/intel: Limit the non-architectural constant_tsc model checks")
Cc: stable@vger.kernel.org # v6.15
Signed-off-by: Suchit Karunakaran suchitkarunakaran@gmail.com
No blank lines between these 3 statements.
Please take all review comments seriously, even if they are nits.
https://lore.kernel.org/lkml/2025073013-stimulus-snowdrift-d28c@gregkh/
Changes since v3:
- Refined changelog
Changes since v2:
- Improve commit message
Changes since v1:
- Fix incorrect logic
Patch-to-patch changes go below the --- line.
You have been provided the same feedback by other folks as well.
https://lore.kernel.org/lkml/61958a3cca40fc9a42b951c68c75f138cab9212e.camel@...
https://lore.kernel.org/lkml/2d30ee37-8069-4443-8a80-5233b3b23f66@intel.com/
If you are not sure, please look at other submissions to the mailing list that do this.
arch/x86/kernel/cpu/intel.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 076eaa41b8c8..6f5bd5dbc249 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -262,7 +262,7 @@ static void early_init_intel(struct cpuinfo_x86 *c) if (c->x86_power & (1 << 8)) { set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
- } else if ((c->x86_vfm >= INTEL_P4_PRESCOTT && c->x86_vfm <= INTEL_P4_WILLAMETTE) ||
- } else if ((c->x86_vfm >= INTEL_P4_PRESCOTT && c->x86_vfm <= INTEL_P4_CEDARMILL) || (c->x86_vfm >= INTEL_CORE_YONAH && c->x86_vfm <= INTEL_IVYBRIDGE)) {
Again, this changes the previous alignment. You do not need the extra space before INTEL_P4_PRESCOTT. Avoiding that would keep both the lines aligned.
https://lore.kernel.org/lkml/30f01900-e79f-4947-b0b4-c4ba29d18084@intel.com/
It's acceptable to ask clarifying questions, but disregarding review comments frustrates reviewers and inclined to ignore future submissions.
set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
}
On Tue, 5 Aug 2025 at 02:07, Sohil Mehta sohil.mehta@intel.com wrote:
Hi Suchit
I would strongly suggest spending more time understanding reviewer feedback and incorporating it before sending another version. Most of the comments below are a repeat from previous reviews by multiple folks.
On 8/4/2025 10:59 AM, Suchit Karunakaran wrote:
Pentium 4's which are INTEL_P4_PRESCOTT (model 0x03) and later have a constant TSC. This was correctly captured until commit fadb6f569b10 ("x86/cpu/intel: Limit the non-architectural constant_tsc model checks"). In that commit, an error was introduced while selecting the last P4 model (0x06) as the upper bound. Model 0x06 was transposed to INTEL_P4_WILLAMETTE, which is just plain wrong. That was presumably a simple typo, probably just copying and pasting the wrong P4 model. Fix the constant TSC logic to cover all later P4 models. End at INTEL_P4_CEDARMILL which accurately corresponds to the last P4 model.
Please use proper spacing and line breaks. Posting this as a single chunk makes it very hard to read.
Fixes: fadb6f569b10 ("x86/cpu/intel: Limit the non-architectural constant_tsc model checks")
Cc: stable@vger.kernel.org # v6.15
Signed-off-by: Suchit Karunakaran suchitkarunakaran@gmail.com
No blank lines between these 3 statements.
Please take all review comments seriously, even if they are nits.
https://lore.kernel.org/lkml/2025073013-stimulus-snowdrift-d28c@gregkh/
Changes since v3:
- Refined changelog
Changes since v2:
- Improve commit message
Changes since v1:
- Fix incorrect logic
Patch-to-patch changes go below the --- line.
You have been provided the same feedback by other folks as well.
https://lore.kernel.org/lkml/61958a3cca40fc9a42b951c68c75f138cab9212e.camel@...
https://lore.kernel.org/lkml/2d30ee37-8069-4443-8a80-5233b3b23f66@intel.com/
If you are not sure, please look at other submissions to the mailing list that do this.
arch/x86/kernel/cpu/intel.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 076eaa41b8c8..6f5bd5dbc249 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -262,7 +262,7 @@ static void early_init_intel(struct cpuinfo_x86 *c) if (c->x86_power & (1 << 8)) { set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
} else if ((c->x86_vfm >= INTEL_P4_PRESCOTT && c->x86_vfm <= INTEL_P4_WILLAMETTE) ||
} else if ((c->x86_vfm >= INTEL_P4_PRESCOTT && c->x86_vfm <= INTEL_P4_CEDARMILL) || (c->x86_vfm >= INTEL_CORE_YONAH && c->x86_vfm <= INTEL_IVYBRIDGE)) {
Again, this changes the previous alignment. You do not need the extra space before INTEL_P4_PRESCOTT. Avoiding that would keep both the lines aligned.
https://lore.kernel.org/lkml/30f01900-e79f-4947-b0b4-c4ba29d18084@intel.com/
It's acceptable to ask clarifying questions, but disregarding review comments frustrates reviewers and inclined to ignore future submissions.
set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); }
Hi Sohil, Thank you very much for your time and the detailed feedback. I sincerely apologize for the repeated mistakes in my submission. It was never my intention to disregard any of the review comments. I was just focused on the commit description and, as a result, was careless in properly incorporating the prior suggestions and formatting requirements. I understand how frustrating this can be, and I truly appreciate the patience shown by you and others throughout the review process. I will take greater care moving forward to ensure that all feedback is fully addressed before resubmitting. Thank you again for your time and guidance.
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