From: Roi Dayan roid@nvidia.com

Miss rule creation is always done with ignore flow level bit set. Older firmwares do not support that. Check FW support before setting the ignore flow level bit.

The issue doesn't exist upstream, it was already fixed by a refactoring commit ae430332557a ("net/mlx5: Refactor multi chains and prios support") which was merged on v5.10.

Fixes: 278d51f24330 ("net/mlx5: E-Switch, Increase number of chains and priorities") Reported-by: Sridhar Samudrala sridhar.samudrala@intel.com Signed-off-by: Roi Dayan roid@nvidia.com Signed-off-by: Saeed Mahameed saeedm@nvidia.com --- drivers/net/ethernet/mellanox/mlx5/core/esw/chains.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/chains.c b/drivers/net/ethernet/mellanox/mlx5/core/esw/chains.c index 029001040737..b801825b3292 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/chains.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/chains.c @@ -419,7 +419,9 @@ mlx5_esw_chains_add_miss_rule(struct fdb_chain *fdb_chain, struct mlx5_flow_destination dest = {}; struct mlx5_flow_act act = {};

- act.flags = FLOW_ACT_IGNORE_FLOW_LEVEL | FLOW_ACT_NO_APPEND; + act.flags = FLOW_ACT_NO_APPEND; + if (fdb_ignore_flow_level_supported(esw)) + act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL; act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST; dest.type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE; dest.ft = next_fdb;