From: Zachary Zhang zhangzg@marvell.com

commit 91a2968e245d6ba616db37001fa1a043078b1a65 usptream.

The PCIE I/O and MEM resource allocation mechanism is that root bus goes through the following steps:

1. Check PCI bridges' range and computes I/O and Mem base/limits.

2. Sort all subordinate devices I/O and MEM resource requirements and allocate the resources and writes/updates subordinate devices' requirements to PCI bridges I/O and Mem MEM/limits registers.

Currently, PCI Aardvark driver only handles the second step and lacks the first step, so there is an I/O and MEM resource allocation failure when using a PCI switch. This commit fixes that by sizing bridges before doing the resource allocation.

Fixes: 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver") Signed-off-by: Zachary Zhang zhangzg@marvell.com [Thomas: edit commit log.] Signed-off-by: Thomas Petazzoni thomas.petazzoni@bootlin.com Signed-off-by: Lorenzo Pieralisi lorenzo.pieralisi@arm.com Cc: stable@vger.kernel.org --- drivers/pci/host/pci-aardvark.c | 1 + 1 file changed, 1 insertion(+)

diff --git a/drivers/pci/host/pci-aardvark.c b/drivers/pci/host/pci-aardvark.c index d0867a311f42..806fa836b2d6 100644 --- a/drivers/pci/host/pci-aardvark.c +++ b/drivers/pci/host/pci-aardvark.c @@ -951,6 +951,7 @@ static int advk_pcie_probe(struct platform_device *pdev)

bus = bridge->bus;

+ pci_bus_size_bridges(bus); pci_bus_assign_resources(bus);

list_for_each_entry(child, &bus->children, node)