Add "mediatek,mt8195-ufshci" to the of_device_id table to enable support for MediaTek MT8195/MT8395 UFS host controller. This matches the device node entry in the MT8195/MT8395 device tree and allows proper driver binding.
Signed-off-by: Macpaul Lin macpaul.lin@mediatek.com --- drivers/ufs/host/ufs-mediatek.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c index 182f58d0c9db..e1dbf0231c5e 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -50,6 +50,7 @@ static const struct ufs_dev_quirk ufs_mtk_dev_fixups[] = {
static const struct of_device_id ufs_mtk_of_match[] = { { .compatible = "mediatek,mt8183-ufshci" }, + { .compatible = "mediatek,mt8195-ufshci" }, {}, }; MODULE_DEVICE_TABLE(of, ufs_mtk_of_match);
Add 'mediatek,mt8195-ufshci' to compatible list. Update clocks and clock-names constraints to allow one to eight entries. Introduce 'mediatek,ufs-disable-mcq' property to disable MCQ (Multi-Circular Queue). Update conditional schema for mt8195 requiring eight 'clocks' and eight 'clock-names'.
Signed-off-by: Macpaul Lin macpaul.lin@mediatek.com --- .../devicetree/bindings/ufs/mediatek,ufs.yaml | 49 ++++++++++++++++--- 1 file changed, 43 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml b/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml index 32fd535a514a..9d6bcf735920 100644 --- a/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml @@ -9,21 +9,20 @@ title: Mediatek Universal Flash Storage (UFS) Controller maintainers: - Stanley Chu stanley.chu@mediatek.com
-allOf: - - $ref: ufs-common.yaml - properties: compatible: enum: - mediatek,mt8183-ufshci - mediatek,mt8192-ufshci + - mediatek,mt8195-ufshci
clocks: - maxItems: 1 + minItems: 1 + maxItems: 8
clock-names: - items: - - const: ufs + minItems: 1 + maxItems: 8
phys: maxItems: 1 @@ -33,6 +32,11 @@ properties:
vcc-supply: true
+ mediatek,ufs-disable-mcq: + $ref: /schemas/types.yaml#/definitions/flag + description: The mask to disable MCQ (Multi-Circular Queue) for UFS host. + type: boolean + required: - compatible - clocks @@ -43,6 +47,39 @@ required:
unevaluatedProperties: false
+allOf: + - $ref: ufs-common.yaml + + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt8195-ufshci + then: + properties: + clocks: + minItems: 8 + maxItems: 8 + clock-names: + items: + - const: ufs + - const: ufs_aes + - const: ufs_tick + - const: unipro_sysclk + - const: unipro_tick + - const: unipro_mp_bclk + - const: ufs_tx_symbol + - const: ufs_mem_sub + else: + properties: + clocks: + minItems: 1 + maxItems: 1 + clock-names: + items: + - const: ufs + examples: - | #include <dt-bindings/clock/mt8183-clk.h>
Hi,
Thanks for your patch.
FYI: kernel test robot notices the stable kernel rule is not satisfied.
The check is based on https://www.kernel.org/doc/html/latest/process/stable-kernel-rules.html#opti...
Rule: add the tag "Cc: stable@vger.kernel.org" in the sign-off area to have the patch automatically included in the stable tree. Subject: [PATCH 2/3] dt-bindings: ufs: mediatek,ufs: add MT8195 compatible and update clock nodes Link: https://lore.kernel.org/stable/20250718082719.653228-2-macpaul.lin%40mediate...
On Fri, Jul 18, 2025 at 04:27:17PM +0800, Macpaul Lin wrote:
Add 'mediatek,mt8195-ufshci' to compatible list. Update clocks and clock-names constraints to allow one to eight entries. Introduce 'mediatek,ufs-disable-mcq' property to disable MCQ (Multi-Circular Queue). Update conditional schema for mt8195 requiring eight 'clocks' and eight 'clock-names'.
Don't just describe the diff, we can read it. Describe why you are making the changes. How is the new h/w different (or the same).
Signed-off-by: Macpaul Lin macpaul.lin@mediatek.com
.../devicetree/bindings/ufs/mediatek,ufs.yaml | 49 ++++++++++++++++--- 1 file changed, 43 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml b/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml index 32fd535a514a..9d6bcf735920 100644 --- a/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml @@ -9,21 +9,20 @@ title: Mediatek Universal Flash Storage (UFS) Controller maintainers:
- Stanley Chu stanley.chu@mediatek.com
-allOf:
- $ref: ufs-common.yaml
properties: compatible: enum: - mediatek,mt8183-ufshci - mediatek,mt8192-ufshci
- mediatek,mt8195-ufshciclocks:
- maxItems: 1
- minItems: 1
- maxItems: 8
clock-names:
- items:
- const: ufs
- minItems: 1
- maxItems: 8
phys: maxItems: 1 @@ -33,6 +32,11 @@ properties: vcc-supply: true
- mediatek,ufs-disable-mcq:
- $ref: /schemas/types.yaml#/definitions/flag
- description: The mask to disable MCQ (Multi-Circular Queue) for UFS host.
- type: boolean
Seems this was undocumented, but already in use. That should be a separate patch.
required:
- compatible
- clocks
@@ -43,6 +47,39 @@ required: unevaluatedProperties: false +allOf:
- $ref: ufs-common.yaml
- if:
properties:compatible:contains:enum:- mediatek,mt8195-ufshci- then:
properties:clocks:minItems: 8maxItems: 8clock-names:items:- const: ufs- const: ufs_aes- const: ufs_tick- const: unipro_sysclk- const: unipro_tick- const: unipro_mp_bclk- const: ufs_tx_symbol- const: ufs_mem_sub- else:
properties:clocks:minItems: 1
1 is already the minimum. Drop.
maxItems: 1clock-names:items:- const: ufsexamples:
- | #include <dt-bindings/clock/mt8183-clk.h>
-- 2.45.2
From: Rice Lee ot_riceyj.lee@mediatek.com
Add a UFS host controller interface (UFSHCI) node to mt8195.dtsi. Introduce the 'mediatek,ufs-disable-mcq' property to allow disabling Multiple Circular Queue (MCQ) support.
Signed-off-by: Rice Lee ot_riceyj.lee@mediatek.com Signed-off-by: Eric Lin ht.lin@mediatek.com Signed-off-by: Macpaul Lin macpaul.lin@mediatek.com --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 25 ++++++++++++++++++++++++ 1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index dd065b1bf94a..8877953ce292 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1430,6 +1430,31 @@ mmc2: mmc@11250000 { status = "disabled"; };
+ ufshci: ufshci@11270000 { + compatible = "mediatek,mt8195-ufshci"; + reg = <0 0x11270000 0 0x2300>; + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH 0>; + phys = <&ufsphy>; + clocks = <&infracfg_ao CLK_INFRA_AO_AES_UFSFDE>, + <&infracfg_ao CLK_INFRA_AO_AES>, + <&infracfg_ao CLK_INFRA_AO_UFS_TICK>, + <&infracfg_ao CLK_INFRA_AO_UNIPRO_SYS>, + <&infracfg_ao CLK_INFRA_AO_UNIPRO_TICK>, + <&infracfg_ao CLK_INFRA_AO_UFS_MP_SAP_B>, + <&infracfg_ao CLK_INFRA_AO_UFS_TX_SYMBOL>, + <&infracfg_ao CLK_INFRA_AO_PERI_UFS_MEM_SUB>; + clock-names = "ufs", "ufs_aes", "ufs_tick", + "unipro_sysclk", "unipro_tick", + "unipro_mp_bclk", "ufs_tx_symbol", + "ufs_mem_sub"; + freq-table-hz = <0 0>, <0 0>, <0 0>, + <0 0>, <0 0>, <0 0>, + <0 0>, <0 0>; + + mediatek,ufs-disable-mcq; + status = "disabled"; + }; + lvts_mcu: thermal-sensor@11278000 { compatible = "mediatek,mt8195-lvts-mcu"; reg = <0 0x11278000 0 0x1000>;
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