Double ! or !! are normally required to get 0 or 1 out of a expression. A
comparision always returns 0 or 1 and hence there is no need to apply double !
over it again.
Signed-off-by: Viresh Kumar <viresh.kumar(a)linaro.org>
---
kernel/power/suspend.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/kernel/power/suspend.c b/kernel/power/suspend.c
index 62ee437..90b3d93 100644
--- a/kernel/power/suspend.c
+++ b/kernel/power/suspend.c
@@ -39,7 +39,7 @@ static const struct platform_suspend_ops *suspend_ops;
static bool need_suspend_ops(suspend_state_t state)
{
- return !!(state > PM_SUSPEND_FREEZE);
+ return state > PM_SUSPEND_FREEZE;
}
static DECLARE_WAIT_QUEUE_HEAD(suspend_freeze_wait_head);
--
1.7.12.rc2.18.g61b472e
Hi,
Here is version 2 of fix to armv7-m build failure in sigreturn_codes.S.
It is based on Dave's suggestion on [1]. Basically it set
arch to arm4t explicitly if CONFIG_CPU_THUMBONLY is set.
That enables both arm and thumb opcodes and code merged with
the rest of image.
Version 1 [2] used conditional compilation.
Fix was tested
linux-next with efm32_defconfig build (along with few other fixes)
rmk-next BE/LE arndale build/boot and LTP rt_sigaction0? tests run
Dave, I've added your name with Suggested-by tag, please
let me know if it is not OK with you, I'll remove it then.
Uwe, is it possible for you to test that this fix runs on
efm32? Sorry, for multiple requests.
To address concern about fragility of proposed solution
I looked binutils bfd/elf32-arm.c
https://sourceware.org/git/?p=binutils.git;a=blob;f=bfd/elf32-arm.c;h=5af16…
Attributes merge deals with couple things:
Tag_CPU_arch: tag_cpu_arch_combine function deals with it
and from its tables it seems that v4t is compatible with
any latter version and resulting value will come from
latter version. I.e v4t and v7 (v7m) would merge fine.
Tag_CPU_arch_profile: since in case of '.arch armv4t'
profile attribute is not generated it is merged fine
with any other profile. Unlike in case of
'.arch armv7a' and '.arch armv7m' profile values would
be 'Application' and 'Microcontroller' and those
conflict.
Above logic seems to be universal, so other linkers
may follow it too. So it seems it is good to use
'.arch armv4t' with armv7m code.
Thanks,
Victor
[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2013-November/210631.…
[2] http://lists.infradead.org/pipermail/linux-arm-kernel/2013-November/210393.…
Victor Kamensky (1):
ARM: signal: fix armv7-m build issue in sigreturn_codes.S
arch/arm/kernel/sigreturn_codes.S | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
--
1.8.1.4
ARM_PATCH_PHYS_VIRT is enabled by default for clps711x systems
Introduction of this config as default will enable phy-to-virt and
virt-to-phy translation function at boot and module loading time
and enforce dynamic reallocation of memory.
This config is mutually exclusive to XIP_KERNEL, which is used in
systems with NOR flash devices
Requesting platform maintainers to evaluate the changes on the
board and comment on the changes, as I dont have the board for
testing.
Signed-off-by: panchaxari <panchaxari.prasannamurthy(a)linaro.org>
Cc: Linus Walleij <linux.walleij(a)linaro.org>
Cc: Alexander Shiyan <shc_work(a)mail.ru>
Cc: Russell King <linux(a)arm.linux.org.uk>
Cc: Olof Johansson <olof(a)lixom.net>
Cc: linux-arm-kernel(a)lists.infradead.org
---
arch/arm/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 1ad6fb6..dff1c81 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -372,6 +372,7 @@ config ARCH_CLPS711X
bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
select ARCH_REQUIRE_GPIOLIB
select AUTO_ZRELADDR
+ select ARM_PATCH_PHYS_VIRT
select CLKDEV_LOOKUP
select CLKSRC_MMIO
select COMMON_CLK
--
1.7.10.4
From: Jean Pihet <jean.pihet(a)newoldbits.com>
This patch implements the functions required for the perf registers API,
allowing the perf tool to interface kernel register dumps with libunwind
in order to provide userspace backtracing.
Only the general purpose user space registers are exported, i.e.:
PERF_REG_ARM_X0,
...
PERF_REG_ARM_X28,
PERF_REG_ARM_FP,
PERF_REG_ARM_LR,
PERF_REG_ARM_SP,
PERF_REG_ARM_PC
and not the PERF_REG_ARM_V* registers.
Dependencies:
. if present, libunwind >= 1.1 is needed to prevent a segfault when
parsing the dwarf info,
. libunwind needs to be configured with --enable-debug-frame. Note:
--enable-debug-frame is automatically selected on ARM, NOT on ARM64.
The generated perf binary has been tested on ARMv8 (using the
foundation model simulator) and x86_64, using the following commands:
perf record -g [fp,dwarf] -- <binary>
perf report --sort symbol --call-graph --stdio
Jean Pihet (2):
ARM64: perf: add support for perf registers API
ARM64: perf: wire up perf_regs and unwind support
arch/arm64/Kconfig | 2 +
arch/arm64/include/uapi/asm/Kbuild | 1 +
arch/arm64/include/uapi/asm/perf_regs.h | 40 ++++++++++++++
arch/arm64/kernel/Makefile | 1 +
arch/arm64/kernel/perf_regs.c | 29 ++++++++++
tools/perf/arch/arm64/Makefile | 7 +++
tools/perf/arch/arm64/include/perf_regs.h | 88 +++++++++++++++++++++++++++++++
tools/perf/arch/arm64/util/dwarf-regs.c | 81 ++++++++++++++++++++++++++++
tools/perf/arch/arm64/util/unwind.c | 82 ++++++++++++++++++++++++++++
tools/perf/config/Makefile | 6 +++
10 files changed, 337 insertions(+)
create mode 100644 arch/arm64/include/uapi/asm/perf_regs.h
create mode 100644 arch/arm64/kernel/perf_regs.c
create mode 100644 tools/perf/arch/arm64/Makefile
create mode 100644 tools/perf/arch/arm64/include/perf_regs.h
create mode 100644 tools/perf/arch/arm64/util/dwarf-regs.c
create mode 100644 tools/perf/arch/arm64/util/unwind.c
--
1.7.11.7
hi all:
I use arm cortex A9 smp with GIC v1 system.
And my kernel is 3.8.13.
I have some questions:
1. From GIc v1 spec, we can modify irq priority.
(ICDIPRn, Interrupt Priority Rigisters)
how could we do that in kernel? Did kernel provide any API of Irq
to reach that goal?
2. From Gic V1 spec, we can assign 1 irq to multi-core.
(ICDIPTRn, Interrupt Processor Targets Registers)
Is there similar API in kernel to let 1 irq possibility to be
handled by multi-cores?
Appreciate your help in advance,