linaro-kernel December 2013

linaro-kernel@lists.linaro.org

83 participants
265 discussions

[PATCH] mfd: wm8994: Allow modular build

by Mark Brown

From: Mark Brown <broonie(a)linaro.org> The interfaces that used to be built in only (interrupts IIRC) no longer are so allow the driver to be built as a module fixing arm64 allmodconfig builds. Signed-off-by: Mark Brown <broonie(a)linaro.org> --- drivers/mfd/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 49bb445d846a..920ddfd85faa 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -1170,11 +1170,11 @@ config MFD_WM8350_I2C selected to enable support for the functionality of the chip. config MFD_WM8994 - bool "Wolfson Microelectronics WM8994" + tristate "Wolfson Microelectronics WM8994" select MFD_CORE select REGMAP_I2C select REGMAP_IRQ - depends on I2C=y + depends on I2C help The WM8994 is a highly integrated hi-fi CODEC designed for smartphone applicatiosn. As well as audio functionality it -- 1.8.5.1

11 years

[RFC PATCH] KVM: arm/arm64: Clarify KVM_ARM_VCPU_INIT api

by Christoffer Dall

There is nothing technically or semantically wrong with calling KVM_ARM_VCPU_INIT more than once, and even calling this on a VCPU after the VCPU has been executed. It just happens that user space will need a way to reset the VCPU or put the VCPU back in PSCI power-off mode after the VM has run, for example when driving a system reset from user space. Clarify that it is perfectly fine to use this API for that purpose. Cc: Peter Maydell <peter.maydell(a)linaro.org> Signed-off-by: Christoffer Dall <christoffer.dall(a)linaro.org> --- Documentation/virtual/kvm/api.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/virtual/kvm/api.txt b/Documentation/virtual/kvm/api.txt index aad3244..d813a61 100644 --- a/Documentation/virtual/kvm/api.txt +++ b/Documentation/virtual/kvm/api.txt @@ -2341,6 +2341,11 @@ return ENOEXEC for that vcpu. Note that because some registers reflect machine topology, all vcpus should be created before this ioctl is invoked. +Calling this a second time on a VCPU will reset the cpu registers to +their initial values and can be used with the feature bits to change the +CPU state, for example to put the CPU into power off mode from user +space. + Possible features: - KVM_ARM_VCPU_POWER_OFF: Starts the CPU in a power-off state. Depends on KVM_CAP_ARM_PSCI. -- 1.8.5

11 years

[PATCH] tty: xuartps: Fix build when SYSRQ is disabled

by Mark Brown

From: Mark Brown <broonie(a)linaro.org> The sysrq field in struct uart_port is only defined when SERIAL_CORE_CONSOLE or SUPPORT_SYSRQ are selected but the driver uses the field unconditionally, causing build failures if they aren't (as happens when doing an arm64 allmodconfig). Make the usage conditional as well. Signed-off-by: Mark Brown <broonie(a)linaro.org> --- drivers/tty/serial/xilinx_uartps.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/tty/serial/xilinx_uartps.c b/drivers/tty/serial/xilinx_uartps.c index e46e9f3f19b9..17de38064b2a 100644 --- a/drivers/tty/serial/xilinx_uartps.c +++ b/drivers/tty/serial/xilinx_uartps.c @@ -240,6 +240,7 @@ static irqreturn_t xuartps_isr(int irq, void *dev_id) continue; } +#if defined(CONFIG_SERIAL_CORE_CONSOLE) || defined(SUPPORT_SYSRQ) /* * uart_handle_sysrq_char() doesn't work if * spinlocked, for some reason @@ -253,6 +254,7 @@ static irqreturn_t xuartps_isr(int irq, void *dev_id) } spin_lock(&port->lock); } +#endif port->icount.rx++; -- 1.8.5.1

11 years

mainline boot: 31 pass, 0 fail (v3.13-rc4-38-gb0031f2)

by Kevin's boot bot

Automated DT boot report for various ARM defconfigs. Tree/Branch: mainline Git describe: v3.13-rc4-38-gb0031f2 Full Report =========== omap2plus_defconfig ------------------- am335x-boneblack PASS: 0 min 27.9 sec omap3-beagle-xm PASS: 0 min 50.6 sec am335x-bone PASS: 0 min 26.6 sec omap4-panda PASS: 1 min 4.9 sec omap4-panda-es PASS: 1 min 5.1 sec omap3-tobi,3730storm PASS: 0 min 24.4 sec omap3-tobi,3530overo PASS: 0 min 21.7 sec tegra_defconfig --------------- tegra30-beaver PASS: 0 min 17.0 sec imx_v6_v7_defconfig ------------------- imx6dl-wandboard,wand-dual PASS: 0 min 16.9 sec imx6dl-wandboard,wand-solo PASS: 0 min 18.2 sec imx6q-wandboard PASS: 0 min 15.3 sec sunxi_defconfig --------------- sun7i-a20-cubieboard2 PASS: 0 min 12.0 sec mvebu_defconfig --------------- armada-xp-openblocks-ax3-4 PASS: 0 min 21.9 sec armada-370-mirabox PASS: 0 min 20.1 sec multi_v7_defconfig ------------------ ste-snowball PASS: 0 min 29.3 sec tegra30-beaver PASS: 0 min 14.2 sec am335x-boneblack PASS: 0 min 24.7 sec omap3-beagle-xm PASS: 0 min 47.9 sec sun7i-a20-cubieboard2 PASS: 0 min 13.0 sec armada-370-mirabox PASS: 0 min 20.6 sec omap4-panda PASS: 0 min 59.4 sec omap4-panda-es PASS: 1 min 2.9 sec armada-xp-openblocks-ax3-4 PASS: 0 min 22.7 sec imx6dl-wandboard,wand-solo PASS: 0 min 16.5 sec am335x-bone PASS: 0 min 23.5 sec imx6q-wandboard PASS: 0 min 16.8 sec omap3-tobi,3730storm PASS: 0 min 19.7 sec imx6dl-wandboard,wand-dual PASS: 0 min 17.9 sec omap3-tobi,3530overo PASS: 0 min 20.6 sec u8500_defconfig --------------- ste-snowball PASS: 0 min 30.9 sec sama5_defconfig --------------- sama5d35ek PASS: 0 min 17.4 sec

11 years

mainline boot: 31 pass, 0 fail (v3.13-rc4-36-g941ef73)

by Kevin's boot bot

Automated DT boot report for various ARM defconfigs. Tree/Branch: mainline Git describe: v3.13-rc4-36-g941ef73 Full Report =========== omap2plus_defconfig ------------------- am335x-boneblack PASS: 0 min 27.9 sec omap3-beagle-xm PASS: 0 min 50.8 sec am335x-bone PASS: 0 min 26.7 sec omap4-panda PASS: 1 min 3.4 sec omap4-panda-es PASS: 1 min 4.5 sec omap3-tobi,3730storm PASS: 0 min 23.5 sec omap3-tobi,3530overo PASS: 0 min 21.8 sec tegra_defconfig --------------- tegra30-beaver PASS: 0 min 16.9 sec imx_v6_v7_defconfig ------------------- imx6dl-wandboard,wand-dual PASS: 0 min 17.1 sec imx6dl-wandboard,wand-solo PASS: 0 min 18.2 sec imx6q-wandboard PASS: 0 min 16.6 sec sunxi_defconfig --------------- sun7i-a20-cubieboard2 PASS: 0 min 12.1 sec mvebu_defconfig --------------- armada-xp-openblocks-ax3-4 PASS: 0 min 21.9 sec armada-370-mirabox PASS: 0 min 21.1 sec multi_v7_defconfig ------------------ ste-snowball PASS: 0 min 32.0 sec tegra30-beaver PASS: 0 min 14.2 sec am335x-boneblack PASS: 0 min 24.7 sec omap3-beagle-xm PASS: 0 min 51.5 sec sun7i-a20-cubieboard2 PASS: 0 min 13.1 sec armada-370-mirabox PASS: 0 min 20.6 sec omap4-panda PASS: 1 min 0.1 sec omap4-panda-es PASS: 1 min 1.9 sec armada-xp-openblocks-ax3-4 PASS: 0 min 22.9 sec imx6dl-wandboard,wand-solo PASS: 0 min 17.6 sec am335x-bone PASS: 0 min 33.5 sec imx6q-wandboard PASS: 0 min 15.8 sec omap3-tobi,3730storm PASS: 0 min 22.9 sec imx6dl-wandboard,wand-dual PASS: 0 min 17.9 sec omap3-tobi,3530overo PASS: 0 min 20.1 sec u8500_defconfig --------------- ste-snowball PASS: 0 min 27.9 sec sama5_defconfig --------------- sama5d35ek PASS: 0 min 17.3 sec

11 years

mainline boot: 31 pass, 0 fail (v3.13-rc4-21-g0eda402)

by Kevin's boot bot

Automated DT boot report for various ARM defconfigs. Tree/Branch: mainline Git describe: v3.13-rc4-21-g0eda402 Full Report =========== omap2plus_defconfig ------------------- am335x-boneblack PASS: 0 min 27.9 sec omap3-beagle-xm PASS: 0 min 52.5 sec am335x-bone PASS: 0 min 26.6 sec omap4-panda PASS: 1 min 4.4 sec omap4-panda-es PASS: 1 min 6.0 sec omap3-tobi,3730storm PASS: 0 min 23.6 sec omap3-tobi,3530overo PASS: 0 min 21.8 sec tegra_defconfig --------------- tegra30-beaver PASS: 0 min 17.1 sec imx_v6_v7_defconfig ------------------- imx6dl-wandboard,wand-dual PASS: 0 min 16.9 sec imx6dl-wandboard,wand-solo PASS: 0 min 18.4 sec imx6q-wandboard PASS: 0 min 16.5 sec sunxi_defconfig --------------- sun7i-a20-cubieboard2 PASS: 0 min 12.1 sec mvebu_defconfig --------------- armada-xp-openblocks-ax3-4 PASS: 0 min 21.9 sec armada-370-mirabox PASS: 0 min 20.0 sec multi_v7_defconfig ------------------ ste-snowball PASS: 0 min 29.0 sec tegra30-beaver PASS: 0 min 16.8 sec am335x-boneblack PASS: 0 min 29.7 sec omap3-beagle-xm PASS: 0 min 51.9 sec sun7i-a20-cubieboard2 PASS: 0 min 13.1 sec armada-370-mirabox PASS: 0 min 20.7 sec omap4-panda PASS: 1 min 0.9 sec omap4-panda-es PASS: 1 min 4.3 sec armada-xp-openblocks-ax3-4 PASS: 0 min 23.0 sec imx6dl-wandboard,wand-solo PASS: 0 min 17.6 sec am335x-bone PASS: 0 min 23.5 sec imx6q-wandboard PASS: 0 min 16.8 sec omap3-tobi,3730storm PASS: 0 min 22.7 sec imx6dl-wandboard,wand-dual PASS: 0 min 17.8 sec omap3-tobi,3530overo PASS: 0 min 20.2 sec u8500_defconfig --------------- ste-snowball PASS: 0 min 30.6 sec sama5_defconfig --------------- sama5d35ek PASS: 0 min 17.4 sec

11 years

[PATCH v4] ARM64 breakpoint and single step exception hooks

by Sandeepa Prabhu

This patch adds support for breakpoint and single-step exception hooks. v3 version of this patch is published and reviewed with arm64 kdgb and kprobes patch series [1] and [2] [1] http://lwn.net/Articles/570648/ [2] https://lwn.net/Articles/571063/ Changes v3 -> v4: -Incorporated review comments: http://lists.infradead.org/pipermail/linux-arm-kernel/2013-October/207372.h… -Removed unnecessary comments -Added comments for breakpoint re-entrancy & rw locks - Rebased on top of git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64.git Branch:upstream commit ID: dc1ccc48159d63eca5089e507c82c7d22ef60839 (Linux 3.13-rc2) - CCing Jason Wessel, since arm64 kgdb patchset is dependant on this. Sandeepa Prabhu (1): arm64: support single-step and breakpoint handler hooks arch/arm64/include/asm/debug-monitors.h | 21 ++++++++ arch/arm64/kernel/debug-monitors.c | 88 ++++++++++++++++++++++++++++++++- arch/arm64/kernel/entry.S | 2 + 3 files changed, 110 insertions(+), 1 deletion(-) -- 1.8.1.2

11 years

[PATCH 1/6] arm64: Add asm/cpu.h

by Mark Brown

From: Hanjun Guo <hanjun.guo(a)linaro.org> In order to implement both topology and ACPI support we need to define per-CPU data. Signed-off-by: Graeme Gregory <graeme.gregory(a)linaro.org> Signed-off-by: Hanjun Guo <hanjun.guo(a)linaro.org> Signed-off-by: Mark Brown <broonie(a)linaro.org> --- arch/arm64/include/asm/cpu.h | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 arch/arm64/include/asm/cpu.h diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h new file mode 100644 index 000000000000..d67ff011d361 --- /dev/null +++ b/arch/arm64/include/asm/cpu.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2004-2005 ARM Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __ASM_ARM64_CPU_H +#define __ASM_ARM64_CPU_H + +#include <linux/percpu.h> +#include <linux/cpu.h> +#include <linux/topology.h> + +struct cpuinfo_arm { + struct cpu cpu; + u64 cpuid; +#ifdef CONFIG_SMP + unsigned int loops_per_jiffy; +#endif +}; + +DECLARE_PER_CPU(struct cpuinfo_arm, cpu_data); + +#endif -- 1.8.5.1

11 years

[PATCH 2/3] ARM64: perf: wire up perf_regs and unwind support

by jean.pihet＠linaro.org

From: Jean Pihet <jean.pihet(a)linaro.org> This patch hooks in the perf_regs and libunwind code for ARM64. The tools/perf/arch/arm64 is created; it contains the arch specific code for DWARF unwinding. Signed-off-by: Jean Pihet <jean.pihet(a)linaro.org> Cc: Will Deacon <will.deacon(a)arm.com> --- tools/perf/arch/arm64/Makefile | 7 +++ tools/perf/arch/arm64/include/perf_regs.h | 88 +++++++++++++++++++++++++++++++ tools/perf/arch/arm64/util/dwarf-regs.c | 81 ++++++++++++++++++++++++++++ tools/perf/arch/arm64/util/unwind.c | 82 ++++++++++++++++++++++++++++ tools/perf/config/Makefile | 8 ++- 5 files changed, 265 insertions(+), 1 deletion(-) create mode 100644 tools/perf/arch/arm64/Makefile create mode 100644 tools/perf/arch/arm64/include/perf_regs.h create mode 100644 tools/perf/arch/arm64/util/dwarf-regs.c create mode 100644 tools/perf/arch/arm64/util/unwind.c diff --git a/tools/perf/arch/arm64/Makefile b/tools/perf/arch/arm64/Makefile new file mode 100644 index 0000000..fe9b61e --- /dev/null +++ b/tools/perf/arch/arm64/Makefile @@ -0,0 +1,7 @@ +ifndef NO_DWARF +PERF_HAVE_DWARF_REGS := 1 +LIB_OBJS += $(OUTPUT)arch/$(ARCH)/util/dwarf-regs.o +endif +ifndef NO_LIBUNWIND +LIB_OBJS += $(OUTPUT)arch/$(ARCH)/util/unwind.o +endif diff --git a/tools/perf/arch/arm64/include/perf_regs.h b/tools/perf/arch/arm64/include/perf_regs.h new file mode 100644 index 0000000..a8a9683 --- /dev/null +++ b/tools/perf/arch/arm64/include/perf_regs.h @@ -0,0 +1,88 @@ +#ifndef ARCH_PERF_REGS_H +#define ARCH_PERF_REGS_H + +#include <stdlib.h> +#include "../../util/types.h" +#include <asm/perf_regs.h> + +#define PERF_REGS_MASK ((1ULL << PERF_REG_ARM_MAX) - 1) +#define PERF_REG_IP PERF_REG_ARM_PC +#define PERF_REG_SP PERF_REG_ARM_SP + +static inline const char *perf_reg_name(int id) +{ + switch (id) { + case PERF_REG_ARM_X0: + return "x0"; + case PERF_REG_ARM_X1: + return "x1"; + case PERF_REG_ARM_X2: + return "x2"; + case PERF_REG_ARM_X3: + return "x3"; + case PERF_REG_ARM_X4: + return "x4"; + case PERF_REG_ARM_X5: + return "x5"; + case PERF_REG_ARM_X6: + return "x6"; + case PERF_REG_ARM_X7: + return "x7"; + case PERF_REG_ARM_X8: + return "x8"; + case PERF_REG_ARM_X9: + return "x9"; + case PERF_REG_ARM_X10: + return "x10"; + case PERF_REG_ARM_X11: + return "x11"; + case PERF_REG_ARM_X12: + return "x12"; + case PERF_REG_ARM_X13: + return "x13"; + case PERF_REG_ARM_X14: + return "x14"; + case PERF_REG_ARM_X15: + return "x15"; + case PERF_REG_ARM_X16: + return "x16"; + case PERF_REG_ARM_X17: + return "x17"; + case PERF_REG_ARM_X18: + return "x18"; + case PERF_REG_ARM_X19: + return "x19"; + case PERF_REG_ARM_X20: + return "x20"; + case PERF_REG_ARM_X21: + return "x21"; + case PERF_REG_ARM_X22: + return "x22"; + case PERF_REG_ARM_X23: + return "x23"; + case PERF_REG_ARM_X24: + return "x24"; + case PERF_REG_ARM_X25: + return "x25"; + case PERF_REG_ARM_X26: + return "x26"; + case PERF_REG_ARM_X27: + return "x27"; + case PERF_REG_ARM_X28: + return "x28"; + case PERF_REG_ARM_FP: + return "fp"; + case PERF_REG_ARM_SP: + return "sp"; + case PERF_REG_ARM_LR: + return "lr"; + case PERF_REG_ARM_PC: + return "pc"; + default: + return NULL; + } + + return NULL; +} + +#endif /* ARCH_PERF_REGS_H */ diff --git a/tools/perf/arch/arm64/util/dwarf-regs.c b/tools/perf/arch/arm64/util/dwarf-regs.c new file mode 100644 index 0000000..23d319e --- /dev/null +++ b/tools/perf/arch/arm64/util/dwarf-regs.c @@ -0,0 +1,81 @@ +/* + * Mapping of DWARF debug register numbers into register names. + * + * Copyright (C) 2010 Will Deacon, ARM Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <stddef.h> +#include <dwarf-regs.h> + +struct pt_regs_dwarfnum { + const char *name; + unsigned int dwarfnum; +}; + +#define STR(s) #s +#define REG_DWARFNUM_NAME(r, num) {.name = r, .dwarfnum = num} +#define GPR_DWARFNUM_NAME(num) \ + {.name = STR(%r##num), .dwarfnum = num} +#define REG_DWARFNUM_END {.name = NULL, .dwarfnum = 0} + +/* + * Reference: + * http://infocenter.arm.com/help/topic/com.arm.doc.ihi0057b/IHI0057B_aadwarf6… + */ +static const struct pt_regs_dwarfnum regdwarfnum_table[] = { + GPR_DWARFNUM_NAME(0), + GPR_DWARFNUM_NAME(1), + GPR_DWARFNUM_NAME(2), + GPR_DWARFNUM_NAME(3), + GPR_DWARFNUM_NAME(4), + GPR_DWARFNUM_NAME(5), + GPR_DWARFNUM_NAME(6), + GPR_DWARFNUM_NAME(7), + GPR_DWARFNUM_NAME(8), + GPR_DWARFNUM_NAME(9), + GPR_DWARFNUM_NAME(10), + GPR_DWARFNUM_NAME(11), + GPR_DWARFNUM_NAME(12), + GPR_DWARFNUM_NAME(13), + GPR_DWARFNUM_NAME(14), + GPR_DWARFNUM_NAME(15), + GPR_DWARFNUM_NAME(16), + GPR_DWARFNUM_NAME(17), + GPR_DWARFNUM_NAME(18), + GPR_DWARFNUM_NAME(19), + GPR_DWARFNUM_NAME(20), + GPR_DWARFNUM_NAME(21), + GPR_DWARFNUM_NAME(22), + GPR_DWARFNUM_NAME(23), + GPR_DWARFNUM_NAME(24), + GPR_DWARFNUM_NAME(25), + GPR_DWARFNUM_NAME(26), + GPR_DWARFNUM_NAME(27), + GPR_DWARFNUM_NAME(28), + REG_DWARFNUM_NAME("%fp", 29), + REG_DWARFNUM_NAME("%lr", 30), + REG_DWARFNUM_NAME("%sp", 31), + REG_DWARFNUM_NAME("%pc", 32), + REG_DWARFNUM_END, +}; + +/** + * get_arch_regstr() - lookup register name from it's DWARF register number + * @n: the DWARF register number + * + * get_arch_regstr() returns the name of the register in struct + * regdwarfnum_table from it's DWARF register number. If the register is not + * found in the table, this returns NULL; + */ +const char *get_arch_regstr(unsigned int n) +{ + const struct pt_regs_dwarfnum *roff; + for (roff = regdwarfnum_table; roff->name != NULL; roff++) + if (roff->dwarfnum == n) + return roff->name; + return NULL; +} diff --git a/tools/perf/arch/arm64/util/unwind.c b/tools/perf/arch/arm64/util/unwind.c new file mode 100644 index 0000000..490bd5b --- /dev/null +++ b/tools/perf/arch/arm64/util/unwind.c @@ -0,0 +1,82 @@ + +#include <errno.h> +#include <libunwind.h> +#include "perf_regs.h" +#include "../../util/unwind.h" + +int unwind__arch_reg_id(int regnum) +{ + switch (regnum) { + case UNW_AARCH64_X0: + return PERF_REG_ARM_X0; + case UNW_AARCH64_X1: + return PERF_REG_ARM_X1; + case UNW_AARCH64_X2: + return PERF_REG_ARM_X2; + case UNW_AARCH64_X3: + return PERF_REG_ARM_X3; + case UNW_AARCH64_X4: + return PERF_REG_ARM_X4; + case UNW_AARCH64_X5: + return PERF_REG_ARM_X5; + case UNW_AARCH64_X6: + return PERF_REG_ARM_X6; + case UNW_AARCH64_X7: + return PERF_REG_ARM_X7; + case UNW_AARCH64_X8: + return PERF_REG_ARM_X8; + case UNW_AARCH64_X9: + return PERF_REG_ARM_X9; + case UNW_AARCH64_X10: + return PERF_REG_ARM_X10; + case UNW_AARCH64_X11: + return PERF_REG_ARM_X11; + case UNW_AARCH64_X12: + return PERF_REG_ARM_X12; + case UNW_AARCH64_X13: + return PERF_REG_ARM_X13; + case UNW_AARCH64_X14: + return PERF_REG_ARM_X14; + case UNW_AARCH64_X15: + return PERF_REG_ARM_X15; + case UNW_AARCH64_X16: + return PERF_REG_ARM_X16; + case UNW_AARCH64_X17: + return PERF_REG_ARM_X17; + case UNW_AARCH64_X18: + return PERF_REG_ARM_X18; + case UNW_AARCH64_X19: + return PERF_REG_ARM_X19; + case UNW_AARCH64_X20: + return PERF_REG_ARM_X20; + case UNW_AARCH64_X21: + return PERF_REG_ARM_X21; + case UNW_AARCH64_X22: + return PERF_REG_ARM_X22; + case UNW_AARCH64_X23: + return PERF_REG_ARM_X23; + case UNW_AARCH64_X24: + return PERF_REG_ARM_X24; + case UNW_AARCH64_X25: + return PERF_REG_ARM_X25; + case UNW_AARCH64_X26: + return PERF_REG_ARM_X26; + case UNW_AARCH64_X27: + return PERF_REG_ARM_X27; + case UNW_AARCH64_X28: + return PERF_REG_ARM_X28; + case UNW_AARCH64_X29: + return PERF_REG_ARM_FP; + case UNW_AARCH64_X30: + return PERF_REG_ARM_LR; + case UNW_AARCH64_SP: + return PERF_REG_ARM_SP; + case UNW_AARCH64_PC: + return PERF_REG_ARM_PC; + default: + pr_err("unwind: invalid reg id %d\n", regnum); + return -EINVAL; + } + + return -EINVAL; +} diff --git a/tools/perf/config/Makefile b/tools/perf/config/Makefile index f7d11a8..658295c 100644 --- a/tools/perf/config/Makefile +++ b/tools/perf/config/Makefile @@ -31,11 +31,17 @@ ifeq ($(ARCH),x86_64) endif NO_PERF_REGS := 0 endif + ifeq ($(ARCH),arm) NO_PERF_REGS := 0 LIBUNWIND_LIBS = -lunwind -lunwind-arm endif +ifeq ($(ARCH),arm64) + NO_PERF_REGS := 0 + LIBUNWIND_LIBS = -lunwind -lunwind-aarch64 +endif + ifeq ($(NO_PERF_REGS),0) CFLAGS += -DHAVE_PERF_REGS_SUPPORT endif @@ -329,7 +335,7 @@ ifndef NO_LIBUNWIND msg := $(warning No libunwind found, disabling post unwind support. Please install libunwind-dev[el] >= 1.1); NO_LIBUNWIND := 1 else - ifeq ($(ARCH),arm) + ifeq ($(ARCH),$(filter $(ARCH),arm arm64)) $(call feature_check,libunwind-debug-frame) ifneq ($(feature-libunwind-debug-frame), 1) msg := $(warning No debug_frame support found in libunwind); -- 1.7.11.7

11 years

[PATCH 1/3] ARM64: perf: add support for perf registers API

by jean.pihet＠linaro.org

From: Jean Pihet <jean.pihet(a)linaro.org> This patch implements the functions required for the perf registers API, allowing the perf tool to interface kernel register dumps with libunwind in order to provide userspace backtracing. Compat mode is also supported. Only the general purpose user space registers are exported, i.e.: PERF_REG_ARM_X0, ... PERF_REG_ARM_X28, PERF_REG_ARM_FP, PERF_REG_ARM_LR, PERF_REG_ARM_SP, PERF_REG_ARM_PC and not the PERF_REG_ARM_V* registers. Signed-off-by: Jean Pihet <jean.pihet(a)linaro.org> Cc: Will Deacon <will.deacon(a)arm.com> --- arch/arm64/Kconfig | 2 ++ arch/arm64/include/asm/ptrace.h | 1 + arch/arm64/include/uapi/asm/Kbuild | 1 + arch/arm64/include/uapi/asm/perf_regs.h | 40 ++++++++++++++++++++++++++++ arch/arm64/kernel/Makefile | 1 + arch/arm64/kernel/perf_regs.c | 46 +++++++++++++++++++++++++++++++++ 6 files changed, 91 insertions(+) create mode 100644 arch/arm64/include/uapi/asm/perf_regs.h create mode 100644 arch/arm64/kernel/perf_regs.c diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 88c8b6c1..f8609dc 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -28,6 +28,8 @@ config ARM64 select HAVE_HW_BREAKPOINT if PERF_EVENTS select HAVE_MEMBLOCK select HAVE_PERF_EVENTS + select HAVE_PERF_REGS + select HAVE_PERF_USER_STACK_DUMP select IRQ_DOMAIN select MODULES_USE_ELF_RELA select NO_BOOTMEM diff --git a/arch/arm64/include/asm/ptrace.h b/arch/arm64/include/asm/ptrace.h index 0e7fa49..fbb0020 100644 --- a/arch/arm64/include/asm/ptrace.h +++ b/arch/arm64/include/asm/ptrace.h @@ -68,6 +68,7 @@ /* Architecturally defined mapping between AArch32 and AArch64 registers */ #define compat_usr(x) regs[(x)] +#define compat_fp regs[11] #define compat_sp regs[13] #define compat_lr regs[14] #define compat_sp_hyp regs[15] diff --git a/arch/arm64/include/uapi/asm/Kbuild b/arch/arm64/include/uapi/asm/Kbuild index e4b78bd..942376d 100644 --- a/arch/arm64/include/uapi/asm/Kbuild +++ b/arch/arm64/include/uapi/asm/Kbuild @@ -9,6 +9,7 @@ header-y += byteorder.h header-y += fcntl.h header-y += hwcap.h header-y += kvm_para.h +header-y += perf_regs.h header-y += param.h header-y += ptrace.h header-y += setup.h diff --git a/arch/arm64/include/uapi/asm/perf_regs.h b/arch/arm64/include/uapi/asm/perf_regs.h new file mode 100644 index 0000000..06bf360 --- /dev/null +++ b/arch/arm64/include/uapi/asm/perf_regs.h @@ -0,0 +1,40 @@ +#ifndef _ASM_ARM_PERF_REGS_H +#define _ASM_ARM_PERF_REGS_H + +enum perf_event_arm_regs { + PERF_REG_ARM_X0, + PERF_REG_ARM_X1, + PERF_REG_ARM_X2, + PERF_REG_ARM_X3, + PERF_REG_ARM_X4, + PERF_REG_ARM_X5, + PERF_REG_ARM_X6, + PERF_REG_ARM_X7, + PERF_REG_ARM_X8, + PERF_REG_ARM_X9, + PERF_REG_ARM_X10, + PERF_REG_ARM_X11, + PERF_REG_ARM_X12, + PERF_REG_ARM_X13, + PERF_REG_ARM_X14, + PERF_REG_ARM_X15, + PERF_REG_ARM_X16, + PERF_REG_ARM_X17, + PERF_REG_ARM_X18, + PERF_REG_ARM_X19, + PERF_REG_ARM_X20, + PERF_REG_ARM_X21, + PERF_REG_ARM_X22, + PERF_REG_ARM_X23, + PERF_REG_ARM_X24, + PERF_REG_ARM_X25, + PERF_REG_ARM_X26, + PERF_REG_ARM_X27, + PERF_REG_ARM_X28, + PERF_REG_ARM_FP, + PERF_REG_ARM_LR, + PERF_REG_ARM_SP, + PERF_REG_ARM_PC, + PERF_REG_ARM_MAX, +}; +#endif /* _ASM_ARM_PERF_REGS_H */ diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile index 5ba2fd4..dffdd93 100644 --- a/arch/arm64/kernel/Makefile +++ b/arch/arm64/kernel/Makefile @@ -15,6 +15,7 @@ arm64-obj-$(CONFIG_COMPAT) += sys32.o kuser32.o signal32.o \ sys_compat.o arm64-obj-$(CONFIG_MODULES) += arm64ksyms.o module.o arm64-obj-$(CONFIG_SMP) += smp.o smp_spin_table.o +arm64-obj-$(CONFIG_PERF_EVENTS) += perf_regs.o arm64-obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o arm64-obj-$(CONFIG_HAVE_HW_BREAKPOINT)+= hw_breakpoint.o arm64-obj-$(CONFIG_EARLY_PRINTK) += early_printk.o diff --git a/arch/arm64/kernel/perf_regs.c b/arch/arm64/kernel/perf_regs.c new file mode 100644 index 0000000..d5c8fd7 --- /dev/null +++ b/arch/arm64/kernel/perf_regs.c @@ -0,0 +1,46 @@ +#include <linux/errno.h> +#include <linux/kernel.h> +#include <linux/perf_event.h> +#include <linux/bug.h> +#include <asm/perf_regs.h> +#include <asm/ptrace.h> + +u64 perf_reg_value(struct pt_regs *regs, int idx) +{ + if (WARN_ON_ONCE((u32)idx >= PERF_REG_ARM_MAX)) + return 0; + + /* + * Compat (i.e. 32 bit) mode: + * - PC has been set in the pt_regs struct in kernel_entry, + * - Handle FP, SP and LR here. + */ + if (compat_user_mode(regs)) { + if ((u32)idx == PERF_REG_ARM_FP) + return regs->compat_fp; + if ((u32)idx == PERF_REG_ARM_SP) + return regs->compat_sp; + if ((u32)idx == PERF_REG_ARM_LR) + return regs->compat_lr; + } + + return regs->regs[idx]; +} + +#define REG_RESERVED (~((1ULL << PERF_REG_ARM_MAX) - 1)) + +int perf_reg_validate(u64 mask) +{ + if (!mask || mask & REG_RESERVED) + return -EINVAL; + + return 0; +} + +u64 perf_reg_abi(struct task_struct *task) +{ + if (test_tsk_thread_flag(task, TIF_32BIT)) + return PERF_SAMPLE_REGS_ABI_32; + else + return PERF_SAMPLE_REGS_ABI_64; +} -- 1.7.11.7

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linaro-kernel December 2013