linaro-kernel May 2013

linaro-kernel@lists.linaro.org

69 participants
72 discussions

[PATCH V5 0/5] Queue work on power efficient wq

by Viresh Kumar

This patchset was called: "Create sched_select_cpu() and use it for workqueues" for the first three versions. Earlier discussions over v3, v2 and v1 can be found here: https://lkml.org/lkml/2013/3/18/364 http://lists.linaro.org/pipermail/linaro-dev/2012-November/014344.html http://www.mail-archive.com/linaro-dev@lists.linaro.org/msg13342.html V4 is here: https://lkml.org/lkml/2013/3/31/55 Workqueues can be performance or power oriented. For performance we may want to keep them running on a single cpu, so that it remains cache hot. For power we can give scheduler the liberty to choose target cpu for running work handler. Later one (Power oriented WQ) can be achieved if the workqueue is allocated with WQ_UNBOUND flag. Enabling CONFIG_WQ_POWER_EFFICIENT will set 'wq_power_efficient' to 'true'. Setting 'power_efficient' boot param will override value of 'wq_power_efficient' variable. When 'wq_power_efficient' is set to 'true', we will convert WQ_POWER_EFFICIENT flag to WQ_UNBOUND on wq allocation. And so scheduler will have the liberty to choose where to run this work. Here we are migrating few users of workqueues to WQ_POWER_EFFICIENT. These drivers are found to be very much active on idle or lightly busy system and using WQ_POWER_EFFICIENT for these gave impressive results. These would be used in power saving mode only if relevant configs are enabled at compile time or in bootargs. Otherwise behavior is unchanged. Setup: ----- - ARM Vexpress TC2 - big.LITTLE CPU - Core 0-1: A15, 2-4: A7 - rootfs: linaro-ubuntu-devel This patchset has been tested on a big LITTLE system (heterogeneous) but is useful for all other homogeneous systems as well. During these tests audio was played in background using aplay. Results: ------- Cluster A15 Energy Cluster A7 Energy Total ------------------------- ----------------------- ------ Without this patchset (Energy in Joules): --------------------------------------------------- 0.151162 2.183545 2.334707 0.223730 2.687067 2.910797 0.289687 2.732702 3.022389 0.454198 2.745908 3.200106 0.495552 2.746465 3.242017 Average: 0.322866 2.619137 2.942003 With this patchset (Energy in Joules): ----------------------------------------------- 0.226421 2.283658 2.510079 0.151361 2.236656 2.388017 0.197726 2.249849 2.447575 0.221915 2.229446 2.451361 0.347098 2.257707 2.604805 Average: 0.2289042 2.2514632 2.4803674 Above tests are repeated multiple times and events are tracked using trace-cmd and analysed using kernelshark. And it was easily noticeable that idle time for many cpus has increased considerably, which eventually saved some power. V4->V5: ------- - Created new wq flag: WQ_POWER_EFFICIENT, config option: CONFIG_WQ_POWER_EFFICIENT and kernel param workqueue.power_efficient. - Created few system wide workqueues aligned towards power saving. V3->V4: ------- - Dropped changes to kernel/sched directory and hence sched_select_non_idle_cpu(). - Dropped queue_work_on_any_cpu() - Created system_freezable_unbound_wq - Changed all patches accordingly. V2->V3: ------- - Dropped changes into core queue_work() API, rather create *_on_any_cpu() APIs - Dropped running timers migration patch as that was broken - Migrated few users of workqueues to use *_on_any_cpu() APIs. Viresh Kumar (5): workqueues: Introduce new flag WQ_POWER_EFFICIENT for power oriented workqueues workqueue: Add system wide power_efficient workqueues PHYLIB: queue work on system_power_efficient_wq block: queue work on power efficient wq fbcon: queue work on power efficient wq Documentation/kernel-parameters.txt | 17 +++++++++++++++++ block/blk-core.c | 3 ++- block/blk-ioc.c | 3 ++- block/genhd.c | 12 ++++++++---- drivers/net/phy/phy.c | 9 +++++---- drivers/video/console/fbcon.c | 2 +- include/linux/workqueue.h | 10 ++++++++++ kernel/power/Kconfig | 19 +++++++++++++++++++ kernel/workqueue.c | 24 +++++++++++++++++++++++- 9 files changed, 87 insertions(+), 12 deletions(-) -- 1.7.12.rc2.18.g61b472e

10 years, 11 months

[PATCH 0/2] Add LCD backlight and LCD enable gpios pins to dp-controller DT node

by Vikas Sajjan

This patch series adds LCD backlight and LCD enable gpios pins to dp-controller DT node of exynos5250-smdk5250 and parsing of these gpio pins in exynos-dp driver tested on exynos5250-smdk5250 Board. rebased on kgene-next branch of https://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git/ Vikas Sajjan (2): video: exynos_dp: Add parsing of gpios pins to exynos-dp driver ARM: dts: Add LCD backlight and LCD enable gpios pins to dp-controller DT node arch/arm/boot/dts/exynos5250-smdk5250.dts | 3 ++ drivers/video/exynos/exynos_dp_core.c | 45 +++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+) -- 1.7.9.5

10 years, 11 months

[PATCH V2] arm64: KVM: Fix HCR_EL2 and VTCR_EL2 configuration bits

by Pranavkumar Sawargaonkar

This patch does following fixes: 1. Make HCR_* flags as unsigned long long constants Reason : By default, compiler assumes numeric constants as signed hence sign extending it when assigned to unsigned variable such as hcr_el2 (in VCPU context). This accidently sets HCR_ID and HCR_CD making entire guest memory non-cacheable. On real HW, this breaks Stage2 ttbl walks and also breaks VirtIO. 2. VTCR_EL2_ORGN0_WBWA and VTCR_EL2_IRGN0_WBWA macros. Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar(a)linaro.org> Signed-off-by: Anup Patel <anup.patel(a)linaro.org> --- arch/arm64/include/asm/kvm_arm.h | 73 +++++++++++++++++++------------------- 1 file changed, 37 insertions(+), 36 deletions(-) diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h index 8ced0ca..14ead69 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -18,44 +18,45 @@ #ifndef __ARM64_KVM_ARM_H__ #define __ARM64_KVM_ARM_H__ +#include <linux/const.h> #include <asm/types.h> /* Hyp Configuration Register (HCR) bits */ -#define HCR_ID (1 << 33) -#define HCR_CD (1 << 32) +#define HCR_ID (UL(0x1) << 33) +#define HCR_CD (UL(0x1) << 32) #define HCR_RW_SHIFT 31 -#define HCR_RW (1 << HCR_RW_SHIFT) -#define HCR_TRVM (1 << 30) -#define HCR_HCD (1 << 29) -#define HCR_TDZ (1 << 28) -#define HCR_TGE (1 << 27) -#define HCR_TVM (1 << 26) -#define HCR_TTLB (1 << 25) -#define HCR_TPU (1 << 24) -#define HCR_TPC (1 << 23) -#define HCR_TSW (1 << 22) -#define HCR_TAC (1 << 21) -#define HCR_TIDCP (1 << 20) -#define HCR_TSC (1 << 19) -#define HCR_TID3 (1 << 18) -#define HCR_TID2 (1 << 17) -#define HCR_TID1 (1 << 16) -#define HCR_TID0 (1 << 15) -#define HCR_TWE (1 << 14) -#define HCR_TWI (1 << 13) -#define HCR_DC (1 << 12) -#define HCR_BSU (3 << 10) -#define HCR_BSU_IS (1 << 10) -#define HCR_FB (1 << 9) -#define HCR_VA (1 << 8) -#define HCR_VI (1 << 7) -#define HCR_VF (1 << 6) -#define HCR_AMO (1 << 5) -#define HCR_IMO (1 << 4) -#define HCR_FMO (1 << 3) -#define HCR_PTW (1 << 2) -#define HCR_SWIO (1 << 1) -#define HCR_VM (1) +#define HCR_RW (UL(0x1) << HCR_RW_SHIFT) +#define HCR_TRVM (UL(0x1) << 30) +#define HCR_HCD (UL(0x1) << 29) +#define HCR_TDZ (UL(0x1) << 28) +#define HCR_TGE (UL(0x1) << 27) +#define HCR_TVM (UL(0x1) << 26) +#define HCR_TTLB (UL(0x1) << 25) +#define HCR_TPU (UL(0x1) << 24) +#define HCR_TPC (UL(0x1) << 23) +#define HCR_TSW (UL(0x1) << 22) +#define HCR_TAC (UL(0x1) << 21) +#define HCR_TIDCP (UL(0x1) << 20) +#define HCR_TSC (UL(0x1) << 19) +#define HCR_TID3 (UL(0x1) << 18) +#define HCR_TID2 (UL(0x1) << 17) +#define HCR_TID1 (UL(0x1) << 16) +#define HCR_TID0 (UL(0x1) << 15) +#define HCR_TWE (UL(0x1) << 14) +#define HCR_TWI (UL(0x1) << 13) +#define HCR_DC (UL(0x1) << 12) +#define HCR_BSU (UL(0x3) << 10) +#define HCR_BSU_IS (UL(0x1) << 10) +#define HCR_FB (UL(0x1) << 9) +#define HCR_VA (UL(0x1) << 8) +#define HCR_VI (UL(0x1) << 7) +#define HCR_VF (UL(0x1) << 6) +#define HCR_AMO (UL(0x1) << 5) +#define HCR_IMO (UL(0x1) << 4) +#define HCR_FMO (UL(0x1) << 3) +#define HCR_PTW (UL(0x1) << 2) +#define HCR_SWIO (UL(0x1) << 1) +#define HCR_VM (UL(0x1)) /* * The bits we set in HCR: @@ -111,9 +112,9 @@ #define VTCR_EL2_SH0_MASK (3 << 12) #define VTCR_EL2_SH0_INNER (3 << 12) #define VTCR_EL2_ORGN0_MASK (3 << 10) -#define VTCR_EL2_ORGN0_WBWA (3 << 10) +#define VTCR_EL2_ORGN0_WBWA (1 << 10) #define VTCR_EL2_IRGN0_MASK (3 << 8) -#define VTCR_EL2_IRGN0_WBWA (3 << 8) +#define VTCR_EL2_IRGN0_WBWA (1 << 8) #define VTCR_EL2_SL0_MASK (3 << 6) #define VTCR_EL2_SL0_LVL1 (1 << 6) #define VTCR_EL2_T0SZ_MASK 0x3f -- 1.7.9.5

10 years, 11 months

[PATCH] arm64: mm: Fix operands of clz in __flush_dcache_all

by Anup Patel

From: Sukanto Ghosh <sghosh(a)apm.com> The format of the lower 32-bits of the 64-bit operand to 'dc cisw' is unchanged from ARMv7 architecture and the upper bits are RES0. This implies that the 'way' field of the operand of 'dc cisw' occupies the bit-positions [31 .. (32-A)]. Due to the use of 64-bit extended operands to 'clz', the existing implementation of __flush_dcache_all is incorrectly placing the 'way' field in the bit-positions [63 .. (64-A)]. Signed-off-by: Sukanto Ghosh <sghosh(a)apm.com> Tested-by: Anup Patel <anup.patel(a)linaro.org> --- arch/arm64/mm/cache.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S index abe69b8..48a3860 100644 --- a/arch/arm64/mm/cache.S +++ b/arch/arm64/mm/cache.S @@ -52,7 +52,7 @@ loop1: add x2, x2, #4 // add 4 (line length offset) mov x4, #0x3ff and x4, x4, x1, lsr #3 // find maximum number on the way size - clz x5, x4 // find bit position of way size increment + clz w5, w4 // find bit position of way size increment mov x7, #0x7fff and x7, x7, x1, lsr #13 // extract max number of the index size loop2: -- 1.7.9.5

10 years, 11 months

[ACTIVITY] 2013-04-27 - 2013-05-10

by David Long

=== David Long === === Highlights === * Tixy voiced doubts about the approach I used for uprobes being upstreamable due to some redundancy in the kprobe/uprobe code. We talked about an alternative design which I now have partially implemented. * Helped relocate the Nashua office to its new space. === Plans === * Continue with uprobe/kprobe * Start building systemtap === Issues === * None -dl

10 years, 11 months

[Question] Regard Of IKS Implementation

by Leo Yan

hi Nico & all, After we studied the IKS code, we believe the code is general and smoothly and can almost meet well for our own SoC's requirement; here also have some questions want to confirm with you guys: 1. When outbound core wake up inbound core, the outbound core's thread will sleep until the inbound core use MCPM’s early pork to send IPI; a) Looks like this method somehow is due to TC2 board has long letancy to power on/off cluster and core; right? How about to use polling method? because on our own SoC, the wakenup interval will take _only_ about 10 ~ 20us; b) The inbound core will send IPI to outbound core for the synchronization, but at this point the inbound core's GIC's cpu interface is disabled; so even the core's cpu interface is disabled, can the core send SGI to other cores? c) MCPM's patchset merged for mainline have no related function for early pork, so later will early pork related functions be committed to mainline? 2. Now the switching is an async operation, means after the function bL_switch_request is return back, we cannot say switching has been completed; so we have some concern for it. For example, when switch from A15 core to A7 core, then maybe we want to decrease the voltage so that can save power; if the switching is an async operation, then it maybe introduce the issue is: after return back from the function bL_switch_request, then s/w will decrease the voltage; but at the meantime, the real switching is ongoing on another pair cores. i browser the git log and get to know at the beginning the switching is synced by using kernel's workqueue, later changed to use a dedicated kernel thread with FIFO type; do u think it's better to go ahead to add sync method for switching? 3. After enabled switcher, then it will disable hotplug. Actually current code can support hotplug with IKS; because with IKS, the logical core will map the according physical core id and GIC's interface id, so that it can make sure if the system has hotplugged out which physical core, later the kernel can hotplug in this physical core. So could u give more hints why iks need disable hotplug? -- Thx, Leo Yan

10 years, 11 months

[ACTIVITY] (John Stultz) May 6 - 10

by John Stultz

=== Highlights === * Did a first pass at addressing remapping issue for volatile ranges (still waiting on Minchan's feedback) * Updated Anton's KDB/FIQ patch queues. Pinged Jason and sent the short list out to lkml for feedback. * Cherry-picked the ION code into a dev tree against 3.10 to learn more about it in prep for future discussions. * Reached out to Arnd on ION dma questions. * Updated linaro.android tree to pre-3.10-rc1, ran into some trouble testing since panda wasn't booting, but Tixy helped with testing and Kevin followed up with a solution for panda. * Sent out some requests-for-participation emails for Linux Plumbers Android miniconf * Talked w/ Deepak about drivers/clocksource issues and other planning * Reviewed YongQins's get_user macro fix * Reviewed blueprints and had bi-weekly hangout with android upstreaming team * Reviewed Dmitry's vfat ioctl patch * Reviewed Zoran's suspend watchdog patchset & discussed plans for suspend-time logging === Plans === * Get feedback from Minchan and send volatile ranges to lkml * Probably More LPC minisummit planning * Hopefully more ION research/discussion === Issues === * NA

10 years, 11 months

Fwd: unhandled level 1 translation fault

by Aparna Mandke

Hi, I am using linaro 13.03 image with ARMv8 fast model. I am getting following "unhandled L1 translation fault" exception while executing a test. Is it a known problem? Does anybody know its solution? I am getting the same error while executing perl benchmark from SPEC 2000. Thanks, Aparna [[ 364.733273] jsc[834]: unhandled level 1 translation fault (11) at 0xffffffff874c0120, esr 0x92000005 [ 364.733356] pgd = ffffffc87d22b000 [ 364.733421] [ffffffff874c0120] *pgd=00000008ffeb9003, *pmd=00000008fe78f003, *pte=00a00008fbd74f53 [ 364.733573] [ 364.733631] Pid: 834, comm: jsc [ 364.733716] CPU: 0 Not tainted (3.9.0-1-linaro-vexpress64 #1ubuntu1~ci+130320041336) [ 364.733796] PC is at 0x4f69d4 [ 364.733860] LR is at 0x44cdec [ 364.733933] pc : [<00000000004f69d4>] lr : [<000000000044cdec>] pstate: 60000000 [ 364.734008] sp : 0000007ff1c891f0 [ 364.734070] x29: 0000007ff1c891f0 x28: 0000000000000000 [ 364.734188] x27: 0000007ff1c89db8 x26: 00000000005258a0 [ 364.734308] x25: 0000007f89342fa8 x24: 0000007f874c00c0 [ 364.734428] x23: 0000007ff1c89900 x22: 000000003f66ea48 [ 364.734548] x21: 0000007f89342e00 x20: 0000007f8933a4b0 [ 364.734669] x19: ffffffff874c0100 x18: 0000007ff1c899a0 [ 364.734789] x17: 0000007f8a2ac7d4 x16: 00000000005827b8 [ 364.734908] x15: 0000007f8a0ca590 x14: 0000000000000000 [ 364.735026] x13: 000000000000001f x12: 0000000000000000 [ 364.735144] x11: 0000000000000000 x10: 0000007f89345420 [ 364.735262] x9 : 000000000000000f x8 : 000000000000000f [ 364.735378] x7 : 000000000000000f x6 : 0000007f89353ca0 [ 364.735498] x5 : 0000007f893433e8 x4 : 0000007f89353cc0 [ 364.735618] x3 : 0000007f89353c40 x2 : 0000000000000003 [ 364.735735] x1 : 000000003f66ea48 x0 : 0000000000000000 [ 364.735845]

10 years, 12 months

Panda board not booting w/ pre 3.10-rc1?

by John Stultz

Hey Kevin, Sorry to pester you, but you've always been helpful with these sort of questions. I'm trying to test a pre 3.10-rc1 kernel on panda, and its hanging after "Starting kernel ..." 3.9 boots fine, and I was curious if you had any hints as to what new config magic I need to get things going. Attached are my good/bad configs. thanks -john

10 years, 12 months

[PATCH] arm64: KVM: Fix HCR_EL2 and VTCR_EL2 configuration bits

by Pranavkumar Sawargaonkar

This patch does following fixes: 1. Make HCR_* flags as unsigned long long constants Reason : By default, compiler assumes numeric constants as signed hence sign extending it when assigned to unsigned variable such as hcr_el2 (in VCPU context). This accidently sets HCR_ID and HCR_CD making entire guest memory non-cacheable. On real HW, this breaks Stage2 ttbl walks and also breaks VirtIO. 2. VTCR_EL2_ORGN0_WBWA and VTCR_EL2_IRGN0_WBWA macros. Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar(a)linaro.org> Signed-off-by: Anup Patel <anup.patel(a)linaro.org> --- arch/arm64/include/asm/kvm_arm.h | 73 +++++++++++++++++++------------------- 1 file changed, 37 insertions(+), 36 deletions(-) diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h index 8ced0ca..0a951db 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -18,44 +18,45 @@ #ifndef __ARM64_KVM_ARM_H__ #define __ARM64_KVM_ARM_H__ +#include <linux/const.h> #include <asm/types.h> /* Hyp Configuration Register (HCR) bits */ -#define HCR_ID (1 << 33) -#define HCR_CD (1 << 32) +#define HCR_ID (_AC(0x1, ULL) << 33) +#define HCR_CD (_AC(0x1, ULL) << 32) #define HCR_RW_SHIFT 31 -#define HCR_RW (1 << HCR_RW_SHIFT) -#define HCR_TRVM (1 << 30) -#define HCR_HCD (1 << 29) -#define HCR_TDZ (1 << 28) -#define HCR_TGE (1 << 27) -#define HCR_TVM (1 << 26) -#define HCR_TTLB (1 << 25) -#define HCR_TPU (1 << 24) -#define HCR_TPC (1 << 23) -#define HCR_TSW (1 << 22) -#define HCR_TAC (1 << 21) -#define HCR_TIDCP (1 << 20) -#define HCR_TSC (1 << 19) -#define HCR_TID3 (1 << 18) -#define HCR_TID2 (1 << 17) -#define HCR_TID1 (1 << 16) -#define HCR_TID0 (1 << 15) -#define HCR_TWE (1 << 14) -#define HCR_TWI (1 << 13) -#define HCR_DC (1 << 12) -#define HCR_BSU (3 << 10) -#define HCR_BSU_IS (1 << 10) -#define HCR_FB (1 << 9) -#define HCR_VA (1 << 8) -#define HCR_VI (1 << 7) -#define HCR_VF (1 << 6) -#define HCR_AMO (1 << 5) -#define HCR_IMO (1 << 4) -#define HCR_FMO (1 << 3) -#define HCR_PTW (1 << 2) -#define HCR_SWIO (1 << 1) -#define HCR_VM (1) +#define HCR_RW (_AC(0x1, ULL) << HCR_RW_SHIFT) +#define HCR_TRVM (_AC(0x1, ULL) << 30) +#define HCR_HCD (_AC(0x1, ULL) << 29) +#define HCR_TDZ (_AC(0x1, ULL) << 28) +#define HCR_TGE (_AC(0x1, ULL) << 27) +#define HCR_TVM (_AC(0x1, ULL) << 26) +#define HCR_TTLB (_AC(0x1, ULL) << 25) +#define HCR_TPU (_AC(0x1, ULL) << 24) +#define HCR_TPC (_AC(0x1, ULL) << 23) +#define HCR_TSW (_AC(0x1, ULL) << 22) +#define HCR_TAC (_AC(0x1, ULL) << 21) +#define HCR_TIDCP (_AC(0x1, ULL) << 20) +#define HCR_TSC (_AC(0x1, ULL) << 19) +#define HCR_TID3 (_AC(0x1, ULL) << 18) +#define HCR_TID2 (_AC(0x1, ULL) << 17) +#define HCR_TID1 (_AC(0x1, ULL) << 16) +#define HCR_TID0 (_AC(0x1, ULL) << 15) +#define HCR_TWE (_AC(0x1, ULL) << 14) +#define HCR_TWI (_AC(0x1, ULL) << 13) +#define HCR_DC (_AC(0x1, ULL) << 12) +#define HCR_BSU (_AC(0x3, ULL) << 10) +#define HCR_BSU_IS (_AC(0x1, ULL) << 10) +#define HCR_FB (_AC(0x1, ULL) << 9) +#define HCR_VA (_AC(0x1, ULL) << 8) +#define HCR_VI (_AC(0x1, ULL) << 7) +#define HCR_VF (_AC(0x1, ULL) << 6) +#define HCR_AMO (_AC(0x1, ULL) << 5) +#define HCR_IMO (_AC(0x1, ULL) << 4) +#define HCR_FMO (_AC(0x1, ULL) << 3) +#define HCR_PTW (_AC(0x1, ULL) << 2) +#define HCR_SWIO (_AC(0x1, ULL) << 1) +#define HCR_VM (_AC(0x1, ULL)) /* * The bits we set in HCR: @@ -111,9 +112,9 @@ #define VTCR_EL2_SH0_MASK (3 << 12) #define VTCR_EL2_SH0_INNER (3 << 12) #define VTCR_EL2_ORGN0_MASK (3 << 10) -#define VTCR_EL2_ORGN0_WBWA (3 << 10) +#define VTCR_EL2_ORGN0_WBWA (1 << 10) #define VTCR_EL2_IRGN0_MASK (3 << 8) -#define VTCR_EL2_IRGN0_WBWA (3 << 8) +#define VTCR_EL2_IRGN0_WBWA (1 << 8) #define VTCR_EL2_SL0_MASK (3 << 6) #define VTCR_EL2_SL0_LVL1 (1 << 6) #define VTCR_EL2_T0SZ_MASK 0x3f -- 1.7.9.5

10 years, 12 months

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linaro-kernel May 2013