linaro-kernel March 2014

linaro-kernel@lists.linaro.org

86 participants
221 discussions

[PATCH v2] arm64: topology: Implement basic CPU topology support

by Mark Brown

From: Mark Brown <broonie(a)linaro.org> Add basic CPU topology support to arm64, based on the existing pre-v8 code and some work done by Mark Hambleton. This patch does not implement any topology discovery support since that should be based on information from firmware, it merely implements the scaffolding for integration of topology support in the architecture. No locking of the topology data is done since it is only modified during CPU bringup with external serialisation from the SMP code. The goal is to separate the architecture hookup for providing topology information from the DT parsing in order to ease review and avoid blocking the architecture code (which will be built on by other work) with the DT code review by providing something simple and basic. Following patches will implement support for interpreting topology information from MPIDR and for parsing the DT topology bindings for ARM, similar patches will be needed for ACPI. Signed-off-by: Mark Brown <broonie(a)linaro.org> Acked-by: Mark RUtland <mark.rutland(a)arm.com> --- arch/arm64/Kconfig | 24 ++++++++++ arch/arm64/include/asm/topology.h | 39 ++++++++++++++++ arch/arm64/kernel/Makefile | 1 + arch/arm64/kernel/smp.c | 11 +++++ arch/arm64/kernel/topology.c | 95 +++++++++++++++++++++++++++++++++++++++ 5 files changed, 170 insertions(+) create mode 100644 arch/arm64/include/asm/topology.h create mode 100644 arch/arm64/kernel/topology.c diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 764d682..80e0eb1 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -165,6 +165,30 @@ config SMP If you don't know what to do here, say N. +config CPU_TOPOLOGY + bool "Support CPU topology definition" + depends on SMP + default y + help + Support CPU topology definition, based on configuration + provided by the firmware. + +config SCHED_MC + bool "Multi-core scheduler support" + depends on CPU_TOPOLOGY + help + Multi-core scheduler support improves the CPU scheduler's decision + making when dealing with multi-core CPU chips at a cost of slightly + increased overhead in some places. If unsure say N here. + +config SCHED_SMT + bool "SMT scheduler support" + depends on CPU_TOPOLOGY + help + Improves the CPU scheduler's decision making when dealing with + MultiThreading at a cost of slightly increased overhead in some + places. If unsure say N here. + config NR_CPUS int "Maximum number of CPUs (2-32)" range 2 32 diff --git a/arch/arm64/include/asm/topology.h b/arch/arm64/include/asm/topology.h new file mode 100644 index 0000000..c8a47e8 --- /dev/null +++ b/arch/arm64/include/asm/topology.h @@ -0,0 +1,39 @@ +#ifndef __ASM_TOPOLOGY_H +#define __ASM_TOPOLOGY_H + +#ifdef CONFIG_CPU_TOPOLOGY + +#include <linux/cpumask.h> + +struct cpu_topology { + int thread_id; + int core_id; + int cluster_id; + cpumask_t thread_sibling; + cpumask_t core_sibling; +}; + +extern struct cpu_topology cpu_topology[NR_CPUS]; + +#define topology_physical_package_id(cpu) (cpu_topology[cpu].cluster_id) +#define topology_core_id(cpu) (cpu_topology[cpu].core_id) +#define topology_core_cpumask(cpu) (&cpu_topology[cpu].core_sibling) +#define topology_thread_cpumask(cpu) (&cpu_topology[cpu].thread_sibling) + +#define mc_capable() (cpu_topology[0].cluster_id != -1) +#define smt_capable() (cpu_topology[0].thread_id != -1) + +void init_cpu_topology(void); +void store_cpu_topology(unsigned int cpuid); +const struct cpumask *cpu_coregroup_mask(int cpu); + +#else + +static inline void init_cpu_topology(void) { } +static inline void store_cpu_topology(unsigned int cpuid) { } + +#endif + +#include <asm-generic/topology.h> + +#endif /* _ASM_ARM_TOPOLOGY_H */ diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile index e52bcdc..da1dafb 100644 --- a/arch/arm64/kernel/Makefile +++ b/arch/arm64/kernel/Makefile @@ -21,6 +21,7 @@ arm64-obj-$(CONFIG_EARLY_PRINTK) += early_printk.o arm64-obj-$(CONFIG_ARM64_CPU_SUSPEND) += sleep.o suspend.o arm64-obj-$(CONFIG_JUMP_LABEL) += jump_label.o arm64-obj-$(CONFIG_KGDB) += kgdb.o +arm64-obj-$(CONFIG_CPU_TOPOLOGY) += topology.o obj-y += $(arm64-obj-y) vdso/ obj-m += $(arm64-obj-m) diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index 5070dc3..f0a141d 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -114,6 +114,11 @@ int __cpu_up(unsigned int cpu, struct task_struct *idle) return ret; } +static void smp_store_cpu_info(unsigned int cpuid) +{ + store_cpu_topology(cpuid); +} + /* * This is the secondary CPU boot entry. We're using this CPUs * idle thread stack, but a set of temporary page tables. @@ -152,6 +157,8 @@ asmlinkage void secondary_start_kernel(void) */ notify_cpu_starting(cpu); + smp_store_cpu_info(cpu); + /* * OK, now it's safe to let the boot CPU continue. Wait for * the CPU migration code to notice that the CPU is online @@ -391,6 +398,10 @@ void __init smp_prepare_cpus(unsigned int max_cpus) int err; unsigned int cpu, ncores = num_possible_cpus(); + init_cpu_topology(); + + smp_store_cpu_info(smp_processor_id()); + /* * are we trying to boot more cores than exist? */ diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c new file mode 100644 index 0000000..3e06b0b --- /dev/null +++ b/arch/arm64/kernel/topology.c @@ -0,0 +1,95 @@ +/* + * arch/arm64/kernel/topology.c + * + * Copyright (C) 2011,2013,2014 Linaro Limited. + * + * Based on the arm32 version written by Vincent Guittot in turn based on + * arch/sh/kernel/topology.c + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#include <linux/cpu.h> +#include <linux/cpumask.h> +#include <linux/init.h> +#include <linux/percpu.h> +#include <linux/node.h> +#include <linux/nodemask.h> +#include <linux/sched.h> + +#include <asm/topology.h> + +/* + * cpu topology table + */ +struct cpu_topology cpu_topology[NR_CPUS]; +EXPORT_SYMBOL_GPL(cpu_topology); + +const struct cpumask *cpu_coregroup_mask(int cpu) +{ + return &cpu_topology[cpu].core_sibling; +} + +static void update_siblings_masks(unsigned int cpuid) +{ + struct cpu_topology *cpu_topo, *cpuid_topo = &cpu_topology[cpuid]; + int cpu; + + if (cpuid_topo->cluster_id == -1) { + /* + * DT does not contain topology information for this cpu + * reset it to default behaviour + */ + pr_debug("CPU%u: No topology information configured\n", cpuid); + cpuid_topo->core_id = 0; + cpumask_set_cpu(cpuid, &cpuid_topo->core_sibling); + cpumask_set_cpu(cpuid, &cpuid_topo->thread_sibling); + return; + } + + /* update core and thread sibling masks */ + for_each_possible_cpu(cpu) { + cpu_topo = &cpu_topology[cpu]; + + if (cpuid_topo->cluster_id != cpu_topo->cluster_id) + continue; + + cpumask_set_cpu(cpuid, &cpu_topo->core_sibling); + if (cpu != cpuid) + cpumask_set_cpu(cpu, &cpuid_topo->core_sibling); + + if (cpuid_topo->core_id != cpu_topo->core_id) + continue; + + cpumask_set_cpu(cpuid, &cpu_topo->thread_sibling); + if (cpu != cpuid) + cpumask_set_cpu(cpu, &cpuid_topo->thread_sibling); + } +} + +void store_cpu_topology(unsigned int cpuid) +{ + update_siblings_masks(cpuid); +} + +/* + * init_cpu_topology is called at boot when only one cpu is running + * which prevent simultaneous write access to cpu_topology array + */ +void __init init_cpu_topology(void) +{ + unsigned int cpu; + + /* init core mask and power*/ + for_each_possible_cpu(cpu) { + struct cpu_topology *cpu_topo = &cpu_topology[cpu]; + + cpu_topo->thread_id = -1; + cpu_topo->core_id = -1; + cpu_topo->cluster_id = -1; + cpumask_clear(&cpu_topo->core_sibling); + cpumask_clear(&cpu_topo->thread_sibling); + } +} -- 1.9.0

10 years, 3 months

[PATCH] ASoC: da732x: Replace hw_read usage with snd_soc_read()

by Mark Brown

From: Mark Brown <broonie(a)linaro.org> Pre-merge code was using direct hw_read() calls as an out of framework way of doing volatile register I/O when not using regmap. This has never functioned correctly in mainline due to the regmap conversion, the hw_read() implementation still does caching. In order to facilitate removal of the subsystem level I/O code convert to use snd_soc_read(), there should be no functional impact. Signed-off-by: Mark Brown <broonie(a)linaro.org> --- sound/soc/codecs/da732x.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/sound/soc/codecs/da732x.c b/sound/soc/codecs/da732x.c index 4d1c302..14acb3a 100644 --- a/sound/soc/codecs/da732x.c +++ b/sound/soc/codecs/da732x.c @@ -1297,9 +1297,9 @@ static void da732x_dac_offset_adjust(struct snd_soc_codec *codec) msleep(DA732X_WAIT_FOR_STABILIZATION); /* Check DAC offset sign */ - sign[DA732X_HPL_DAC] = (codec->hw_read(codec, DA732X_REG_HPL_DAC_OFF_CNTL) & + sign[DA732X_HPL_DAC] = snd_soc_read(codec, DA732X_REG_HPL_DAC_OFF_CNTL) & DA732X_HP_DAC_OFF_CNTL_COMPO); - sign[DA732X_HPR_DAC] = (codec->hw_read(codec, DA732X_REG_HPR_DAC_OFF_CNTL) & + sign[DA732X_HPR_DAC] = snd_soc_read(codec, DA732X_REG_HPR_DAC_OFF_CNTL) & DA732X_HP_DAC_OFF_CNTL_COMPO); /* Binary search DAC offset values (both channels at once) */ @@ -1316,10 +1316,10 @@ static void da732x_dac_offset_adjust(struct snd_soc_codec *codec) msleep(DA732X_WAIT_FOR_STABILIZATION); - if ((codec->hw_read(codec, DA732X_REG_HPL_DAC_OFF_CNTL) & + if ((snd_soc_read(codec, DA732X_REG_HPL_DAC_OFF_CNTL) & DA732X_HP_DAC_OFF_CNTL_COMPO) ^ sign[DA732X_HPL_DAC]) offset[DA732X_HPL_DAC] &= ~step; - if ((codec->hw_read(codec, DA732X_REG_HPR_DAC_OFF_CNTL) & + if ((snd_soc_read(codec, DA732X_REG_HPR_DAC_OFF_CNTL) & DA732X_HP_DAC_OFF_CNTL_COMPO) ^ sign[DA732X_HPR_DAC]) offset[DA732X_HPR_DAC] &= ~step; @@ -1360,9 +1360,9 @@ static void da732x_output_offset_adjust(struct snd_soc_codec *codec) msleep(DA732X_WAIT_FOR_STABILIZATION); /* Check output offset sign */ - sign[DA732X_HPL_AMP] = codec->hw_read(codec, DA732X_REG_HPL) & + sign[DA732X_HPL_AMP] = snd_soc_read(codec, DA732X_REG_HPL) & DA732X_HP_OUT_COMPO; - sign[DA732X_HPR_AMP] = codec->hw_read(codec, DA732X_REG_HPR) & + sign[DA732X_HPR_AMP] = snd_soc_read(codec, DA732X_REG_HPR) & DA732X_HP_OUT_COMPO; snd_soc_write(codec, DA732X_REG_HPL, DA732X_HP_OUT_COMP | @@ -1383,10 +1383,10 @@ static void da732x_output_offset_adjust(struct snd_soc_codec *codec) msleep(DA732X_WAIT_FOR_STABILIZATION); - if ((codec->hw_read(codec, DA732X_REG_HPL) & + if ((snd_soc_read(codec, DA732X_REG_HPL) & DA732X_HP_OUT_COMPO) ^ sign[DA732X_HPL_AMP]) offset[DA732X_HPL_AMP] &= ~step; - if ((codec->hw_read(codec, DA732X_REG_HPR) & + if ((snd_soc_read(codec, DA732X_REG_HPR) & DA732X_HP_OUT_COMPO) ^ sign[DA732X_HPR_AMP]) offset[DA732X_HPR_AMP] &= ~step; -- 1.9.0

10 years, 3 months

[PATCH] arm64: topology: Implement basic CPU topology support

by Mark Brown

From: Mark Brown <broonie(a)linaro.org> Add basic CPU topology support to arm64, based on the existing pre-v8 code and some work done by Mark Hambleton. This patch does not implement any topology discovery support since that should be based on information from firmware, it merely implements the scaffolding for integration of topology support in the architecture. No locking of the topology data is done since it is only modified during CPU bringup with external serialisation from the SMP code. The goal is to separate the architecture hookup for providing topology information from the DT parsing in order to ease review and avoid blocking the architecture code (which will be built on by other work) with the DT code review by providing something simple and basic. A following patch will implement support for parsing the DT topology bindings for ARM, similar patches will be needed for ACPI. Signed-off-by: Mark Brown <broonie(a)linaro.org> --- Just posting the first patch for now, I've tweaked the debug output so we don't print errors on missing topology information now but otherwise no changes. I will repost the DT stuff once I've managed to test changes to completely discard the DT topology on error, should be next week if not this. arch/arm64/Kconfig | 24 ++++++++++ arch/arm64/include/asm/topology.h | 39 ++++++++++++++++ arch/arm64/kernel/Makefile | 1 + arch/arm64/kernel/smp.c | 11 +++++ arch/arm64/kernel/topology.c | 95 +++++++++++++++++++++++++++++++++++++++ 5 files changed, 170 insertions(+) create mode 100644 arch/arm64/include/asm/topology.h create mode 100644 arch/arm64/kernel/topology.c diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 764d682..80e0eb1 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -165,6 +165,30 @@ config SMP If you don't know what to do here, say N. +config CPU_TOPOLOGY + bool "Support CPU topology definition" + depends on SMP + default y + help + Support CPU topology definition, based on configuration + provided by the firmware. + +config SCHED_MC + bool "Multi-core scheduler support" + depends on CPU_TOPOLOGY + help + Multi-core scheduler support improves the CPU scheduler's decision + making when dealing with multi-core CPU chips at a cost of slightly + increased overhead in some places. If unsure say N here. + +config SCHED_SMT + bool "SMT scheduler support" + depends on CPU_TOPOLOGY + help + Improves the CPU scheduler's decision making when dealing with + MultiThreading at a cost of slightly increased overhead in some + places. If unsure say N here. + config NR_CPUS int "Maximum number of CPUs (2-32)" range 2 32 diff --git a/arch/arm64/include/asm/topology.h b/arch/arm64/include/asm/topology.h new file mode 100644 index 0000000..c8a47e8 --- /dev/null +++ b/arch/arm64/include/asm/topology.h @@ -0,0 +1,39 @@ +#ifndef __ASM_TOPOLOGY_H +#define __ASM_TOPOLOGY_H + +#ifdef CONFIG_CPU_TOPOLOGY + +#include <linux/cpumask.h> + +struct cpu_topology { + int thread_id; + int core_id; + int cluster_id; + cpumask_t thread_sibling; + cpumask_t core_sibling; +}; + +extern struct cpu_topology cpu_topology[NR_CPUS]; + +#define topology_physical_package_id(cpu) (cpu_topology[cpu].cluster_id) +#define topology_core_id(cpu) (cpu_topology[cpu].core_id) +#define topology_core_cpumask(cpu) (&cpu_topology[cpu].core_sibling) +#define topology_thread_cpumask(cpu) (&cpu_topology[cpu].thread_sibling) + +#define mc_capable() (cpu_topology[0].cluster_id != -1) +#define smt_capable() (cpu_topology[0].thread_id != -1) + +void init_cpu_topology(void); +void store_cpu_topology(unsigned int cpuid); +const struct cpumask *cpu_coregroup_mask(int cpu); + +#else + +static inline void init_cpu_topology(void) { } +static inline void store_cpu_topology(unsigned int cpuid) { } + +#endif + +#include <asm-generic/topology.h> + +#endif /* _ASM_ARM_TOPOLOGY_H */ diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile index e52bcdc..da1dafb 100644 --- a/arch/arm64/kernel/Makefile +++ b/arch/arm64/kernel/Makefile @@ -21,6 +21,7 @@ arm64-obj-$(CONFIG_EARLY_PRINTK) += early_printk.o arm64-obj-$(CONFIG_ARM64_CPU_SUSPEND) += sleep.o suspend.o arm64-obj-$(CONFIG_JUMP_LABEL) += jump_label.o arm64-obj-$(CONFIG_KGDB) += kgdb.o +arm64-obj-$(CONFIG_CPU_TOPOLOGY) += topology.o obj-y += $(arm64-obj-y) vdso/ obj-m += $(arm64-obj-m) diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index 5070dc3..f0a141d 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -114,6 +114,11 @@ int __cpu_up(unsigned int cpu, struct task_struct *idle) return ret; } +static void smp_store_cpu_info(unsigned int cpuid) +{ + store_cpu_topology(cpuid); +} + /* * This is the secondary CPU boot entry. We're using this CPUs * idle thread stack, but a set of temporary page tables. @@ -152,6 +157,8 @@ asmlinkage void secondary_start_kernel(void) */ notify_cpu_starting(cpu); + smp_store_cpu_info(cpu); + /* * OK, now it's safe to let the boot CPU continue. Wait for * the CPU migration code to notice that the CPU is online @@ -391,6 +398,10 @@ void __init smp_prepare_cpus(unsigned int max_cpus) int err; unsigned int cpu, ncores = num_possible_cpus(); + init_cpu_topology(); + + smp_store_cpu_info(smp_processor_id()); + /* * are we trying to boot more cores than exist? */ diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c new file mode 100644 index 0000000..91889d7 --- /dev/null +++ b/arch/arm64/kernel/topology.c @@ -0,0 +1,95 @@ +/* + * arch/arm64/kernel/topology.c + * + * Copyright (C) 2011,2013,2014 Linaro Limited. + * + * Based on the arm32 version written by Vincent Guittot in turn based on + * arch/sh/kernel/topology.c + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#include <linux/cpu.h> +#include <linux/cpumask.h> +#include <linux/init.h> +#include <linux/percpu.h> +#include <linux/node.h> +#include <linux/nodemask.h> +#include <linux/sched.h> + +#include <asm/topology.h> + +/* + * cpu topology table + */ +struct cpu_topology cpu_topology[NR_CPUS]; +EXPORT_SYMBOL_GPL(cpu_topology); + +const struct cpumask *cpu_coregroup_mask(int cpu) +{ + return &cpu_topology[cpu].core_sibling; +} + +static void update_siblings_masks(unsigned int cpuid) +{ + struct cpu_topology *cpu_topo, *cpuid_topo = &cpu_topology[cpuid]; + int cpu; + + if (cpuid_topo->cluster_id == -1) { + /* + * DT does not contain topology information for this cpu + * reset it to default behaviour + */ + pr_dbg("CPU%u: No topology information configured\n", cpuid); + cpuid_topo->core_id = 0; + cpumask_set_cpu(cpuid, &cpuid_topo->core_sibling); + cpumask_set_cpu(cpuid, &cpuid_topo->thread_sibling); + return; + } + + /* update core and thread sibling masks */ + for_each_possible_cpu(cpu) { + cpu_topo = &cpu_topology[cpu]; + + if (cpuid_topo->cluster_id != cpu_topo->cluster_id) + continue; + + cpumask_set_cpu(cpuid, &cpu_topo->core_sibling); + if (cpu != cpuid) + cpumask_set_cpu(cpu, &cpuid_topo->core_sibling); + + if (cpuid_topo->core_id != cpu_topo->core_id) + continue; + + cpumask_set_cpu(cpuid, &cpu_topo->thread_sibling); + if (cpu != cpuid) + cpumask_set_cpu(cpu, &cpuid_topo->thread_sibling); + } +} + +void store_cpu_topology(unsigned int cpuid) +{ + update_siblings_masks(cpuid); +} + +/* + * init_cpu_topology is called at boot when only one cpu is running + * which prevent simultaneous write access to cpu_topology array + */ +void __init init_cpu_topology(void) +{ + unsigned int cpu; + + /* init core mask and power*/ + for_each_possible_cpu(cpu) { + struct cpu_topology *cpu_topo = &cpu_topology[cpu]; + + cpu_topo->thread_id = -1; + cpu_topo->core_id = -1; + cpu_topo->cluster_id = -1; + cpumask_clear(&cpu_topo->core_sibling); + cpumask_clear(&cpu_topo->thread_sibling); + } +} -- 1.9.0

10 years, 3 months

[PATCH 1/3] cpufreq: move call to __find_governor() to cpufreq_init_policy()

by Viresh Kumar

We call __find_governor() during addition of first CPU of every policy to find the last governor used for this CPU before it was hotplugged-out. After that we call cpufreq_parse_governor() in cpufreq_init_policy() either with this governor or default governor. And right after that policy->governor is set to NULL. So, instead of doing this move the relevant parts to cpufreq_init_policy() policy only and initialize policy->governor to NULL at the beginning. Signed-off-by: Viresh Kumar <viresh.kumar(a)linaro.org> --- Hi Saravana, I hope only the first two patches would fix things for you but probably you can test all three. @Rafael: We might need to get these in next rc only as these are more or less fixes. drivers/cpufreq/cpufreq.c | 34 ++++++++++++++++------------------ 1 file changed, 16 insertions(+), 18 deletions(-) diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c index c755b5f..cc4f244 100644 --- a/drivers/cpufreq/cpufreq.c +++ b/drivers/cpufreq/cpufreq.c @@ -879,18 +879,27 @@ err_out_kobj_put: static void cpufreq_init_policy(struct cpufreq_policy *policy) { + struct cpufreq_governor *gov = NULL; struct cpufreq_policy new_policy; int ret = 0; memcpy(&new_policy, policy, sizeof(*policy)); + /* Update governor of new_policy to the governor used before hotplug */ +#ifdef CONFIG_HOTPLUG_CPU + gov = __find_governor(per_cpu(cpufreq_cpu_governor, policy->cpu)); +#endif + if (gov) + pr_debug("Restoring governor %s for cpu %d\n", + policy->governor->name, policy->cpu); + else + gov = CPUFREQ_DEFAULT_GOVERNOR; + + new_policy.governor = gov; + /* Use the default policy if its valid. */ if (cpufreq_driver->setpolicy) - cpufreq_parse_governor(policy->governor->name, - &new_policy.policy, NULL); - - /* assure that the starting sequence is run in cpufreq_set_policy */ - policy->governor = NULL; + cpufreq_parse_governor(gov->name, &new_policy.policy, NULL); /* set default policy */ ret = cpufreq_set_policy(policy, &new_policy); @@ -944,11 +953,11 @@ static struct cpufreq_policy *cpufreq_policy_restore(unsigned int cpu) unsigned long flags; read_lock_irqsave(&cpufreq_driver_lock, flags); - policy = per_cpu(cpufreq_cpu_data_fallback, cpu); - read_unlock_irqrestore(&cpufreq_driver_lock, flags); + policy->governor = NULL; + return policy; } @@ -1036,7 +1045,6 @@ static int __cpufreq_add_dev(struct device *dev, struct subsys_interface *sif, unsigned long flags; #ifdef CONFIG_HOTPLUG_CPU struct cpufreq_policy *tpolicy; - struct cpufreq_governor *gov; #endif if (cpu_is_offline(cpu)) @@ -1094,7 +1102,6 @@ static int __cpufreq_add_dev(struct device *dev, struct subsys_interface *sif, else policy->cpu = cpu; - policy->governor = CPUFREQ_DEFAULT_GOVERNOR; cpumask_copy(policy->cpus, cpumask_of(cpu)); init_completion(&policy->kobj_unregister); @@ -1179,15 +1186,6 @@ static int __cpufreq_add_dev(struct device *dev, struct subsys_interface *sif, blocking_notifier_call_chain(&cpufreq_policy_notifier_list, CPUFREQ_START, policy); -#ifdef CONFIG_HOTPLUG_CPU - gov = __find_governor(per_cpu(cpufreq_cpu_governor, cpu)); - if (gov) { - policy->governor = gov; - pr_debug("Restoring governor %s for cpu %d\n", - policy->governor->name, cpu); - } -#endif - if (!frozen) { ret = cpufreq_add_dev_interface(policy, dev); if (ret) -- 1.7.12.rc2.18.g61b472e

10 years, 3 months

[PATCH v4 0/6] [RFC] Support for creating generic host_bridge from device tree

by Liviu Dudau

This is v4 of my attempt to add support for a generic pci_host_bridge controller created from a description passed in the device tree. Changes from v3: - Dynamically allocate bus_range resource in of_create_pci_host_bridge() - Fix the domain number used when creating child busses. - Changed domain number allocator to use atomic operations. - Use ERR_PTR() to propagate the error out of pci_create_root_bus_in_domain() and of_create_pci_host_bridge(). Changes from v2: - Use range->cpu_addr when calling pci_address_to_pio() - Introduce pci_register_io_range() helper function in order to register io ranges ahead of their conversion to PIO values. This is needed as no information is being stored yet regarding the range mapping, making pci_address_to_pio() fail. Default weak implementation does nothing, to cover the default weak implementation of pci_address_to_pio() that expects direct mapping of physical addresses into PIO values (x86 view). Changes from v1: - Add patch to fix conversion of IO ranges into IO resources. - Added a domain_nr member to pci_host_bridge structure, and a new function to create a root bus in a given domain number. In order to facilitate that I propose changing the order of initialisation between pci_host_bridge and it's related bus in pci_create_root_bus() as sort of a rever of 7b5436635800. This is done in patch 1/4 and 2/4. - Added a simple allocator of domain numbers in drivers/pci/host-bridge.c. The code will first try to get a domain id from of_alias_get_id(..., "pci-domain") and if that fails assign the next unallocated domain id. - Changed the name of the function that creates the generic host bridge from pci_host_bridge_of_init to of_create_pci_host_bridge and exported as GPL symbol. v1 thread here: https://lkml.org/lkml/2014/2/3/380 The following is an edit of the original blurb: Following the discussion started here [1], I now have a proposal for tackling generic support for host bridges described via device tree. It is an initial stab at it, to try to get feedback and suggestions, but it is functional enough that I have PCI Express for arm64 working on an FPGA using the patch that I am also publishing that adds support for PCI for that platform. Looking at the existing architectures that fit the requirements (use of device tree and PCI) yields the powerpc and microblaze as generic enough to make them candidates for conversion. I have a tentative patch for microblaze that I can only compile test it, unfortunately using qemu-microblaze leads to an early crash in the kernel. As Bjorn has mentioned in the previous discussion, the idea is to add to struct pci_host_bridge enough data to be able to reduce the size or remove the architecture specific pci_controller structure. arm64 support actually manages to get rid of all the architecture static data and has no pci_controller structure defined. For host bridge drivers that means a change of API unless architectures decide to provide a compatibility layer (comments here please). In order to initialise a host bridge with the new API, the following example code is sufficient for a _probe() function: static int myhostbridge_probe(struct platform_device *pdev) { int err; struct device_node *dev; struct pci_host_bridge *bridge; struct myhostbridge_port *pp; resource_size_t lastbus; dev = pdev->dev.of_node; if (!of_device_is_available(dev)) { pr_warn("%s: disabled\n", dev->full_name); return -ENODEV; } pp = kzalloc(sizeof(struct myhostbridge_port), GFP_KERNEL); if (!pp) return -ENOMEM; bridge = of_create_pci_host_bridge(&pdev->dev, &myhostbridge_ops, pp); if (IS_ERR(bridge)) { err = PTR_ERR(bridge); goto bridge_create_fail; } err = myhostbridge_setup(bridge->bus); if (err) goto bridge_setup_fail; /* We always enable PCI domains and we keep domain 0 backward * compatible in /proc for video cards */ pci_add_flags(PCI_ENABLE_PROC_DOMAINS); pci_add_flags(PCI_REASSIGN_ALL_BUS | PCI_REASSIGN_ALL_RSRC); lastbus = pci_scan_child_bus(bridge->bus); pci_bus_update_busn_res_end(bridge->bus, lastbus); pci_assign_unassigned_bus_resources(bridge->bus); pci_bus_add_devices(bridge->bus); return 0; bridge_setup_fail: put_device(&bridge->dev); device_unregister(&bridge->dev); bridge_create_fail: kfree(pp); return err; } [1] http://thread.gmane.org/gmane.linux.kernel.pci/25946 Best regards, Liviu Liviu Dudau (6): pci: Introduce pci_register_io_range() helper function. pci: OF: Fix the conversion of IO ranges into IO resources. pci: Create pci_host_bridge before its associated bus in pci_create_root_bus. pci: Introduce a domain number for pci_host_bridge. pci: Use parent domain number when allocating child busses. pci: Add support for creating a generic host_bridge from device tree drivers/of/address.c | 39 +++++++++++++ drivers/pci/host-bridge.c | 139 +++++++++++++++++++++++++++++++++++++++++++++ drivers/pci/probe.c | 72 +++++++++++++++-------- include/linux/of_address.h | 14 +---- include/linux/pci.h | 17 ++++++ 5 files changed, 246 insertions(+), 35 deletions(-) -- 1.9.0

10 years, 3 months

mainline boot: 46 pass, 1 fail (v3.14-rc5-43-g0c0bd34)

by Kevin's boot bot

Automated DT boot report for various ARM defconfigs. Tree/Branch: mainline Git describe: v3.14-rc5-43-g0c0bd34 Failed boot tests (console logs at the end) =========================================== omap5-uevm: FAIL: omap2plus_defconfig Full Report =========== da8xx_omapl_defconfig --------------------- da850-evm PASS: 0 min 15.2 sec omap2plus_defconfig ------------------- legacy,3730xm PASS: 0 min 53.4 sec am335x-boneblack PASS: 0 min 25.6 sec omap3-beagle-xm PASS: 0 min 59.9 sec legacy,3530beagle PASS: 1 min 58.5 sec omap4-panda PASS: 1 min 8.4 sec omap3-overo-tobi PASS: 0 min 23.0 sec am335x-bone PASS: 0 min 27.4 sec omap3-overo-storm-tobi PASS: 0 min 25.3 sec omap5-uevm FAIL: 0 min 31.4 sec omap4-panda-es PASS: 1 min 6.8 sec legacy,3730storm PASS: 0 min 23.3 sec legacy,3530overo PASS: 0 min 21.1 sec multi_lpae_defconfig -------------------- omap5-uevm PASS: 1 min 47.1 sec sun7i-a20-cubieboard2 PASS: 0 min 14.5 sec tegra_defconfig --------------- tegra30-beaver PASS: 0 min 17.0 sec imx_v6_v7_defconfig ------------------- imx6dl-wandboard,wand-dual PASS: 0 min 18.4 sec imx6dl-wandboard,wand-solo PASS: 0 min 18.4 sec imx6q-wandboard PASS: 0 min 17.0 sec msm_defconfig ------------- qcom-apq8074-dragonboard PASS: 1 min 15.7 sec bcm_defconfig ------------- bcm28155-ap PASS: 0 min 58.8 sec sunxi_defconfig --------------- sun7i-a20-cubieboard2 PASS: 0 min 12.7 sec sun4i-a10-cubieboard PASS: 0 min 20.0 sec exynos_defconfig ---------------- exynos5250-arndale PASS: 0 min 30.2 sec multi_v7_defconfig ------------------ ste-snowball PASS: 1 min 20.8 sec tegra30-beaver PASS: 0 min 23.1 sec am335x-boneblack PASS: 0 min 23.2 sec omap3-beagle-xm PASS: 0 min 47.5 sec sun7i-a20-cubieboard2 PASS: 0 min 14.1 sec armada-370-mirabox PASS: 0 min 22.0 sec omap4-panda PASS: 0 min 52.1 sec armada-xp-openblocks-ax3-4 PASS: 0 min 25.0 sec sun4i-a10-cubieboard PASS: 0 min 18.4 sec bcm28155-ap PASS: 1 min 14.8 sec omap3-overo-tobi PASS: 0 min 22.1 sec imx6dl-wandboard,wand-solo PASS: 0 min 17.9 sec am335x-bone PASS: 0 min 26.0 sec omap3-overo-storm-tobi PASS: 0 min 24.0 sec omap5-uevm PASS: 1 min 48.5 sec imx6q-wandboard PASS: 0 min 17.2 sec omap4-panda-es PASS: 0 min 58.5 sec imx6dl-wandboard,wand-dual PASS: 0 min 18.1 sec u8500_defconfig --------------- ste-snowball PASS: 0 min 33.4 sec sama5_defconfig --------------- sama5d35ek PASS: 0 min 17.1 sec davinci_all_defconfig --------------------- legacy,dm365evm PASS: 0 min 16.6 sec mvebu_defconfig --------------- armada-xp-openblocks-ax3-4 PASS: 0 min 22.1 sec armada-370-mirabox PASS: 0 min 20.1 sec Console logs for failures ========================= omap2plus_defconfig ------------------- omap5-uevm: FAIL: last 80 lines of boot log: -------------------------------------------- Connected to omap5uevm console [channel connected] (~$quit to exit) (user:khilman) is already connected ~$hardreset Command(omap5uevm console)> hardreset (user:khilman) Reboot omap5uevm Reboot: omap5uevm ; phidget 1 2 : off, sleep, on 0 U-Boot# found: 002/015 2 ~$off # PYBOOT: Exception: ERROR: Could not break into autoboot. # PYBOOT: Time: 31.38 seconds. # PYBOOT: Result: FAIL

10 years, 4 months

None

by Emanuel Nazetta

10 years, 4 months

[PATCH v4 0/3] [RFC] Add support for PCI in AArch64

by Liviu Dudau

Hi, This patch adds support for PCI to AArch64. It is based on my v4 patch that adds support for creating generic host bridge structure from device tree. With that in place, I was able to boot a platform that has PCIe host bridge support and use a PCIe network card. Changes from v3: - Added Acks accumulated so far ;) - Still carrying Catalin's patch for moving the PCI_IO_BASE until it lands in linux-next or mainline, in order to ease applying the series Changes from v2: - Implement an arch specific version of pci_register_io_range() and pci_address_to_pio(). - Return 1 from pci_proc_domain(). Changes from v1: - Added Catalin's patch for moving the PCI_IO_BASE location and extend its size to 16MB - Integrated Arnd's version of pci_ioremap_io that uses a bitmap for keeping track of assigned IO space and returns an io_offset. At the moment the code is added in arch/arm64 but it can be moved in drivers/pci. - Added a fix for the generic ioport_map() function when !CONFIG_GENERIC_IOMAP as suggested by Arnd. The API used is different from the one used by ARM architecture. There is no pci_common_init_dev() function and no hw_pci structure, as that is no longer needed. Once the last signature is added to the legal agreement, I will post the host bridge driver code that I am using. Meanwhile, here is an example of what the probe function looks like, posted as an example: static int myhostbridge_probe(struct platform_device *pdev) { int err; struct device_node *dev; struct pci_host_bridge *bridge; struct myhostbridge_port *pp; resource_size_t lastbus; dev = pdev->dev.of_node; if (!of_device_is_available(dev)) { pr_warn("%s: disabled\n", dev->full_name); return -ENODEV; } pp = kzalloc(sizeof(struct myhostbridge_port), GFP_KERNEL); if (!pp) return -ENOMEM; bridge = of_create_pci_host_bridge(&pdev->dev, &myhostbridge_ops, pp); if (IS_ERR(bridge)) { err = PTR_ERR(bridge); goto bridge_create_fail; } err = myhostbridge_setup(bridge->bus); if (err) goto bridge_setup_fail; /* We always enable PCI domains and we keep domain 0 backward * compatible in /proc for video cards */ pci_add_flags(PCI_ENABLE_PROC_DOMAINS); pci_add_flags(PCI_REASSIGN_ALL_BUS | PCI_REASSIGN_ALL_RSRC); lastbus = pci_scan_child_bus(bridge->bus); pci_bus_update_busn_res_end(bridge->bus, lastbus); pci_assign_unassigned_bus_resources(bridge->bus); pci_bus_add_devices(bridge->bus); return 0; bridge_setup_fail: put_device(&bridge->dev); device_unregister(&bridge->dev); bridge_create_fail: kfree(pp); return err; } Best regards, Liviu Catalin Marinas (1): arm64: Extend the PCI I/O space to 16MB Liviu Dudau (2): Fix ioport_map() for !CONFIG_GENERIC_IOMAP cases. arm64: Add architecture support for PCI Documentation/arm64/memory.txt | 16 ++-- arch/arm64/Kconfig | 19 ++++- arch/arm64/include/asm/Kbuild | 1 + arch/arm64/include/asm/io.h | 5 +- arch/arm64/include/asm/pci.h | 47 +++++++++++ arch/arm64/kernel/Makefile | 1 + arch/arm64/kernel/pci.c | 178 +++++++++++++++++++++++++++++++++++++++++ include/asm-generic/io.h | 2 +- 8 files changed, 259 insertions(+), 10 deletions(-) create mode 100644 arch/arm64/include/asm/pci.h create mode 100644 arch/arm64/kernel/pci.c -- 1.9.0

10 years, 4 months

[RFC v2 PATCH 0/1] ARM64: KGDB: Add FPSIMD debug support

by vijay.kilari＠gmail.com

From: Vijaya Kumar K <Vijaya.Kumar(a)caviumnetworks.com> Based on ARM64 KGDB support patches, KGDB support for FPSIMD is added. Only debugging of FPSIMD kernel context is supported. This patch requires Ard's patches where in kernel support and below patch for holding thread's fpsimd state. http://permalink.gmane.org/gmane.linux.ports.arm.kernel/277228 So CONFIG_KERNEL_MODE_NEON should be enabled. with this, FPSIMD registers can be viewed or set from gdb tool. Unlike CPU registers, the FPSIMD registers are not saved on exception entry. With the known restriction that FPSIMD should not be touched in interrupt/exception context, in this patch the FPSIMD registers are directly read/written on gdb tool request Here, the FPSIMD registers are read and restored for every FPSIMD register read and write by GDB tool. So this has impact on gdb tool response which is neglible. Other architectures like mips are also implemented similarly v2 changes: - Added API to know thread fpsimd state by checking TIF_FOREIGN_FPSTATE flag. This is based on below patch http://permalink.gmane.org/gmane.linux.ports.arm.kernel/277228 - Allow FPSIMD registers access only when FPSIMD is under use by current thread v1 changes: - Initial patch Tested on ARM64 simulator Vijaya Kumar K (1): ARM64: KGDB: Add FP/SIMD debug support arch/arm64/include/asm/fpsimd.h | 1 + arch/arm64/kernel/fpsimd.c | 5 ++ arch/arm64/kernel/kgdb.c | 105 +++++++++++++++++++++++++-------------- 3 files changed, 73 insertions(+), 38 deletions(-) -- 1.7.9.5

10 years, 4 months

next boot: 46 pass, 1 fail (next-20140303)

by Kevin's boot bot

Automated DT boot report for various ARM defconfigs. Tree/Branch: next Git describe: next-20140303 Failed boot tests (console logs at the end) =========================================== ste-snowball: FAIL: multi_v7_defconfig Full Report =========== da8xx_omapl_defconfig --------------------- da850-evm PASS: 0 min 15.3 sec omap2plus_defconfig ------------------- legacy,3730xm PASS: 0 min 51.4 sec am335x-boneblack PASS: 0 min 25.4 sec omap3-beagle-xm PASS: 1 min 1.6 sec legacy,3530beagle PASS: 1 min 49.6 sec omap4-panda PASS: 1 min 12.2 sec omap3-overo-tobi PASS: 0 min 22.8 sec am335x-bone PASS: 0 min 27.4 sec omap3-overo-storm-tobi PASS: 0 min 22.1 sec omap5-uevm PASS: 1 min 1.4 sec omap4-panda-es PASS: 1 min 5.4 sec legacy,3730storm PASS: 0 min 23.7 sec legacy,3530overo PASS: 0 min 21.1 sec multi_lpae_defconfig -------------------- omap5-uevm PASS: 1 min 44.8 sec sun7i-a20-cubieboard2 PASS: 0 min 14.2 sec tegra_defconfig --------------- tegra30-beaver PASS: 0 min 17.1 sec imx_v6_v7_defconfig ------------------- imx6dl-wandboard,wand-dual PASS: 0 min 18.1 sec imx6dl-wandboard,wand-solo PASS: 0 min 18.3 sec imx6q-wandboard PASS: 0 min 16.5 sec sunxi_defconfig --------------- sun7i-a20-cubieboard2 PASS: 0 min 12.7 sec sun4i-a10-cubieboard PASS: 0 min 17.1 sec bcm_defconfig ------------- bcm28155-ap PASS: 0 min 53.5 sec mvebu_v7_defconfig ------------------ armada-xp-openblocks-ax3-4 PASS: 0 min 22.3 sec armada-370-mirabox PASS: 0 min 20.2 sec exynos_defconfig ---------------- exynos5250-arndale PASS: 0 min 29.2 sec multi_v7_defconfig ------------------ qcom-apq8074-dragonboard PASS: 1 min 14.6 sec ste-snowball FAIL: 0 min 33.4 sec tegra30-beaver PASS: 0 min 19.7 sec am335x-boneblack PASS: 0 min 23.5 sec omap3-beagle-xm PASS: 0 min 52.2 sec sun7i-a20-cubieboard2 PASS: 0 min 14.1 sec armada-370-mirabox PASS: 0 min 22.1 sec omap4-panda PASS: 1 min 3.6 sec armada-xp-openblocks-ax3-4 PASS: 0 min 25.7 sec sun4i-a10-cubieboard PASS: 0 min 18.4 sec bcm28155-ap PASS: 1 min 3.9 sec omap3-overo-tobi PASS: 0 min 22.1 sec imx6dl-wandboard,wand-solo PASS: 0 min 17.5 sec am335x-bone PASS: 0 min 26.3 sec omap3-overo-storm-tobi PASS: 0 min 24.1 sec omap5-uevm PASS: 1 min 49.6 sec imx6q-wandboard PASS: 0 min 16.7 sec omap4-panda-es PASS: 0 min 53.4 sec imx6dl-wandboard,wand-dual PASS: 0 min 17.9 sec u8500_defconfig --------------- ste-snowball PASS: 0 min 33.2 sec sama5_defconfig --------------- sama5d35ek PASS: 0 min 17.0 sec davinci_all_defconfig --------------------- legacy,dm365evm PASS: 0 min 17.0 sec Console logs for failures ========================= multi_v7_defconfig ------------------ ste-snowball: FAIL: last 80 lines of boot log: ---------------------------------------------- (user:khilman) Reboot snowball Reboot: snowball ; ip9258 2 2 : ('off', 6, 'on') , sleep 6, MCDE: startup failed sec_bridge: ISSWAPI_FLUSH_BOOT_CODE: 2 EMMC: 0, MMC: 1 In: serial Out: serial Err: serial Net: smc911x-0 Hit any key to stop autoboot: 1 0 U8500 $ U8500 $ version U8500 $ versionsetenv ethaddr 6e:e6:84:36:8e:9e U-Boot 2009.11 (sept. 19 2011 - 17:03:11) U8500 $ setenv ethaddr 6e:e6:84:36:8e:9esetenv bootargs console=ttyAMA2,115200n8 debug earlyprintk rw root=/dev/mmcblk0p3 rootwait rootfstype=ext4 Can't overwrite "ethaddr" U8500 $ setenv bootargs console=ttyAMA2,115200n8 debug earlyprintk rw root=/dev/mmcblk0p3 rootwait rootfstype=ext4setenv netargs 'setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}::::192.168.1.254:none' U8500 $ setenv netargs 'setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}::::192.168.1.254:none'if test -n ${initenv}; then run initenv; fi U8500 $ if test -n ${initenv}; then run initenv; fiif test -n ${preboot}; then run preboot; fi U8500 $ if test -n ${preboot}; then run preboot; fisetenv autoload no; setenv autoboot no U8500 $ setenv autoload no; setenv autoboot nodhcp U8500 $ dhcp smc911x: detected LAN9221 controller smc911x: phy initialized smc911x: MAC 6e:e6:84:36:8e:9e BOOTP broadcast 1 BOOTP broadcast 2 DHCP client bound to address 192.168.1.159 U8500 $setenv serverip 192.168.1.2 setenv serverip 192.168.1.2 U8500 $ if test -n ${netargs}; then run netargs; fi if test -n ${netargs}; then run netargs; fi U8500 $tftp 0x00800000 192.168.1.2:tmp/snowball-S7Aaig/tmpxTiBdf-uImage tftp 0x00800000 192.168.1.2:tmp/snowball-S7Aaig/tmpxTiBdf-uImage smc911x: detected LAN9221 controller smc911x: phy initialized smc911x: MAC 6e:e6:84:36:8e:9e Using smc911x-0 device TFTP from server 192.168.1.2; our IP address is 192.168.1.159 Filename 'tmp/snowball-S7Aaig/tmpxTiBdf-uImage'. Load address: 0x800000 Loading: *################################################################# ################################################################# ################################################################# ################################################################# ##################################################### done Bytes transferred = 4587769 (4600f9 hex) U8500 $ printenv bootargs printenv bootargs bootargs=console=ttyAMA2,115200n8 debug earlyprintk rw root=/dev/mmcblk0p3 rootwait rootfstype=ext4 ip=192.168.1.159:192.168.1.2:192.168.1.254:255.255.255.0::::192.168.1.254:none U8500 $ bootm 0x00800000 bootm 0x00800000 ## Booting kernel from Legacy Image at 00800000 ... Image Name: Linux Image Type: ARM Linux Kernel Image (uncompressed) Data Size: 4587705 Bytes = 4.4 MB Load Address: 00008000 Entry Point: 00008000 Loading Kernel Image ... OK OK Starting kernel ... ~$off # PYBOOT: Exception: kernel: ERROR: did not start booting. # PYBOOT: Time: 33.42 seconds. # PYBOOT: Result: FAIL

10 years, 4 months

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

linaro-kernel March 2014