On Friday 01 July 2011 20:26:54 Dave Martin wrote:
On Fri, Jul 01, 2011 at 03:38:48PM +0100, Tixy wrote:
Finally, is it safe to assume that a single kernel binary will never support both v5 and v6 hardware? What about v4 and v5?
I think it's "too hard" to support v6 and pre-v6 in the same kernel, so such configurations are not really supported.
Other than that, I'm not too sure. Nico or someone may know.
We can have common kernels for v6+v7, and we can have common kernels for v3+v4+v5, iirc.
I was also looking at the Instruction Set Attribute Register in CP15, these give me the exact information I want, but I suspect that determining their availability will be as difficult as writing code to probe the features I'm interested in (ARM/Thumb interworking).
v7 processors and a few earlier processors have these registers.
If it's the ARM/Thumb interworking behaviour you're interested in, note that the kernel is a non-interworking environment, and cannot be built for (or contain any) Thumb code on ARMv4T. So those instructions really shouldn't make a difference unless the kernel is buggy.
The interworking behaviour is uniform for ARMv5(T) and above, but since kernels built in Thumb cannot run on pre-v7, and kernels built in ARM cannot (or certainly should not) contain any Thumb code, these niceties may not matter.
Another variable would be endianess, if the goal is to support every single possibility.
Arnd