On 04/23/2013 12:37 AM, Nicolas Pitre wrote:
On Mon, 22 Apr 2013, Leo Yan wrote:
On 04/20/2013 05:34 AM, Nicolas Pitre wrote:
[ Looping in Achin and Lorenzo ]
On Fri, 19 Apr 2013, Leo Yan wrote:
hi Nico & all,
We are do some profiling on TC2 board for low power mode, and found there have some long latency for the core/cluster's power on sequence, so want to confirm below questions:
- From our profiling result, we found if the core_A send IPI to core_B
and the core_B run into the function bL_entry_point (or the function mcpm_entry_point in your later patches for mainline) will take about 954us, it's really a long interval.
Is core_B in a different cluster than core_A? It is a known fact that powering up a cluster has far greater latency than simply pulling a core out of reset.
Yes, core_B is a different cluster than core_A.
If there have other cores in the same core_B's cluster are powered on, then we can see the power on interval will take about 300us ~ 600us, but the worst case is core_B is the first man of the cluster, then usually it will take about 900+us (seldom even more than 1ms).
Yes, that is known. Stabilizing the voltage when powering up a whole cluster on TC2 apparently takes that long. That is a characteristic that depends on the hardware implementation.
The switcher code on top of MCPM implements a notification mechanism to let the outbound CPU continue processing work until the inbound is fully operational and ready to take over in order to mitigate this latency.
Do u mean the outbound core will remain in cache coherency so that the inbound core can snoop the outbound core's cache; after a while the inbound core will notify the outbound core to flush cache, clear SMP bit and really run into the low power mode?
However when a cluster is turned off resulting from cpuidle decisions, then waking up from idle mode does take that long for the system to resume. This has caused issues with the serial console losing characters when large strings are pasted for example, overflowing the 32 byte FIFO before the UART interrupt is serviced.
Nicolas