ARMv8 allows AArch64-EL0 to execute cache maintenance instructions (eg, by setting SCTLR_EL1.UCI). It looks like the current ARMv8 kernel doesn't support the above feature.
Is there any plan in Linux for allowing AArch64_EL0 to perform cache-line operations?
Regards, Rajan
ARMv8 allows AArch64-EL0 to execute cache maintenance instructions (eg, by setting SCTLR_EL1.UCI). It looks like the current ARMv8 kernel doesn't support the above feature.
Is there any plan in Linux for allowing AArch64_EL0 to perform cache-line operations?
Regards, Rajan [Apologies for resending this mail, as previously I probably sent to linaro-kernel only]
On Wed, Apr 30, 2014 at 02:01:38PM +0530, Rajan Srivastava wrote:
ARMv8 allows AArch64-EL0 to execute cache maintenance instructions (eg, by setting SCTLR_EL1.UCI). It looks like the current ARMv8 kernel doesn't support the above feature.
Where have you looked and came up to this conclusion?
I am referring to ARM for ARMv8-A, "ARM DDI 0487A.a_errata_2013_Q3 (ID100313)", section D8.2.79 'System Control Register (EL1)'.
Thanks, Rajan
----------------------------------------
Date: Wed, 30 Apr 2014 11:58:20 +0100 From: catalin.marinas@arm.com To: rajan_srivastava@hotmail.com CC: linaro-kernel@lists.linaro.org; linux-arm-kernel@lists.infradead.org Subject: Re: ARMv8: Allowing user space to perform cache-maintenance
On Wed, Apr 30, 2014 at 02:01:38PM +0530, Rajan Srivastava wrote:
ARMv8 allows AArch64-EL0 to execute cache maintenance instructions (eg, by setting SCTLR_EL1.UCI). It looks like the current ARMv8 kernel doesn't support the above feature.
Where have you looked and came up to this conclusion?
-- Catalin
linaro-kernel@lists.linaro.org
-
Catalin Marinas -
catalin.marinas＠arm.com
-
Rajan Srivastava