From: Richard Zhu hongxing.zhu@nxp.com
[ Upstream commit 051d9eb403887bb11852b7a4f744728a6a4b1b58 ]
On i.MX7/iMX8MM/iMX8MQ, the initialized default value of PERST bit(BIT3) of SRC_PCIEPHY_RCR is 1b'1. But i.MX8MP has one inversed default value 1b'0 of PERST bit.
And the PERST bit should be kept 1b'1 after power and clocks are stable. So fix the i.MX8MP PCIe PHY PERST support here.
Fixes: e08672c03981 ("reset: imx7: Add support for i.MX8MP SoC") Signed-off-by: Richard Zhu hongxing.zhu@nxp.com Reviewed-by: Philipp Zabel p.zabel@pengutronix.de Tested-by: Marek Vasut marex@denx.de Tested-by: Richard Leitner richard.leitner@skidata.com Tested-by: Alexander Stein alexander.stein@ew.tq-group.com Signed-off-by: Philipp Zabel p.zabel@pengutronix.de Link: https://lore.kernel.org/r/1661845564-11373-5-git-send-email-hongxing.zhu@nxp... Signed-off-by: Sasha Levin sashal@kernel.org --- drivers/reset/reset-imx7.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/reset/reset-imx7.c b/drivers/reset/reset-imx7.c index 185a333df66c..d2408725eb2c 100644 --- a/drivers/reset/reset-imx7.c +++ b/drivers/reset/reset-imx7.c @@ -329,6 +329,7 @@ static int imx8mp_reset_set(struct reset_controller_dev *rcdev, break;
case IMX8MP_RESET_PCIE_CTRL_APPS_EN: + case IMX8MP_RESET_PCIEPHY_PERST: value = assert ? 0 : bit; break; }