On Fri, Sep 27, 2019 at 08:26:32AM -0700, Raj, Ashok wrote:
On Fri, Sep 27, 2019 at 07:54:57AM -0500, Bjorn Helgaas wrote:
[+cc Andrew, Alex, Ashok]
Please cc people who commented on previous versions of a patch. I added them for you here.
This is probably fine, but I'm waiting to see if Ashok gets a response from the chipset folks. Hopefully he can ack this as a simple typo fix.
On Wed, Sep 18, 2019 at 03:16:52PM +0200, Steffen Liebergeld wrote:
According to documentation [0] the correct offset for the Upstream Peer Decode Configuration Register (UPDCR) is 0x1014. It was previously defined as 0x1114.
Finally someone in the HW team was able to lookup the documentation and it has stayed at 0x1014 per internal documentation. Apparently the genesis is about 10 years ago :-)... so it took some time to hunt this from the team.
that's the final answer :-)
So I *think* that's an ack for this patch, right?
Commit d99321b63b1f intends to enforce isolation between PCI devices allowing them to be put into separate IOMMU groups. Due to the wrong register offset the intended isolation was not fully enforced. This is fixed with this patch.
Please note that I did not test this patch because I have no hardware that implements this register.
[0] https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/4th-... (page 325)
Fixes: d99321b63b1f ("PCI: Enable quirks for PCIe ACS on Intel PCH root ports") Reviewed-by: Andrew Murray andrew.murray@arm.com Signed-off-by: Steffen Liebergeld steffen.liebergeld@kernkonzept.com
And I suppose this should have a stable tag. d99321b63b1f appeared in v3.15.
I applied this as below to pci/virtualization for v5.5, thanks!
commit e50992e80279 Author: Steffen Liebergeld steffen.liebergeld@kernkonzept.com Date: Wed Sep 18 15:16:52 2019 +0200
PCI: Fix Intel ACS quirk UPDCR register address
According to documentation [0] the correct offset for the Upstream Peer Decode Configuration Register (UPDCR) is 0x1014. It was previously defined as 0x1114.
d99321b63b1f ("PCI: Enable quirks for PCIe ACS on Intel PCH root ports") intended to enforce isolation between PCI devices allowing them to be put into separate IOMMU groups. Due to the wrong register offset the intended isolation was not fully enforced. This is fixed with this patch.
Please note that I did not test this patch because I have no hardware that implements this register.
[0] https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/4th-... (page 325) Fixes: d99321b63b1f ("PCI: Enable quirks for PCIe ACS on Intel PCH root ports") Link: https://lore.kernel.org/r/7a3505df-79ba-8a28-464c-88b83eefffa6@kernkonzept.c... Signed-off-by: Steffen Liebergeld steffen.liebergeld@kernkonzept.com Signed-off-by: Bjorn Helgaas bhelgaas@google.com Reviewed-by: Andrew Murray andrew.murray@arm.com Acked-by: Ashok Raj ashok.raj@intel.com Cc: stable@vger.kernel.org # v3.15+
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 4e5048cb5ec6..23508c359296 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -4713,7 +4713,7 @@ int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags) #define INTEL_BSPR_REG_BPPD (1 << 9)
/* Upstream Peer Decode Configuration Register */ -#define INTEL_UPDCR_REG 0x1114 +#define INTEL_UPDCR_REG 0x1014 /* 5:0 Peer Decode Enable bits */ #define INTEL_UPDCR_REG_MASK 0x3f