Hi YF,
The calling to kmem_cache_alloc for level 2 page table allocation may run in atomic context, and it fails sometimes when DMA32 zone runs out of memory.
Since Mediatek IOMMU hardware support at most 35bit PA in page table,
s/Mediatek/MediaTek/ s/support/supports/
so add a quirk to allow the PA of level 2 pgtable support bit35.
35bits PA, right?
...snip...
phys = virt_to_phys(table);
- if (phys != (arm_v7s_iopte)phys) {
- if (phys != (arm_v7s_iopte)phys &&
!(cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT)) {
I have one question while reading this.
If IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT is set, it means that the phys can be up to 35 bits. In aarch64, kmalloc() could return up to 52 bits PA (e.g., ARM64_PA_BITS_52=y)
How do we guarantee that phys is safe (<= 35 bits) in this case? For example: When IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT is set, the platform guarantees its PAs are at most 35 bits?
Thanks, Miles
/* Doesn't fit in PTE */ dev_err(dev, "Page table does not fit in PTE: %pa", &phys); goto out_free;@@ -457,9 +464,14 @@ static arm_v7s_iopte arm_v7s_install_table(arm_v7s_iopte *table, arm_v7s_iopte curr, struct io_pgtable_cfg *cfg) {
- phys_addr_t phys = virt_to_phys(table); arm_v7s_iopte old, new;
- new = virt_to_phys(table) | ARM_V7S_PTE_TYPE_TABLE;
- new = phys | ARM_V7S_PTE_TYPE_TABLE;
- if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT)
new = to_iopte_mtk(phys, new, cfg);- if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS) new |= ARM_V7S_ATTR_NS_TABLE;
@@ -778,6 +790,7 @@ static phys_addr_t arm_v7s_iova_to_phys(struct io_pgtable_ops *ops, static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg, void *cookie) {
- slab_flags_t slab_flag = ARM_V7S_TABLE_SLAB_FLAGS; struct arm_v7s_io_pgtable *data;
if (cfg->ias > (arm_v7s_is_mtk_enabled(cfg) ? 34 : ARM_V7S_ADDR_BITS)) @@ -788,7 +801,8 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg, if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS | IO_PGTABLE_QUIRK_NO_PERMS |
IO_PGTABLE_QUIRK_ARM_MTK_EXT))
IO_PGTABLE_QUIRK_ARM_MTK_EXT |IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT))/* If ARM_MTK_4GB is enabled, the NO_PERMS is also expected. */ @@ -801,10 +815,12 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg, return NULL; spin_lock_init(&data->split_lock);
- if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT)
slab_flag = 0;
ARM_V7S_TABLE_SLAB_FLAGS, NULL);
slab_flag, NULL);diff --git a/include/linux/io-pgtable.h b/include/linux/io-pgtable.h index 86af6f0a00a2..7ed15ad4710c 100644 --- a/include/linux/io-pgtable.h +++ b/include/linux/io-pgtable.h @@ -74,17 +74,22 @@ struct io_pgtable_cfg { * to support up to 35 bits PA where the bit32, bit33 and bit34 are * encoded in the bit9, bit4 and bit5 of the PTE respectively. *
* IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT: (ARM v7s format) MediaTek IOMMUs* extend the translation table support up to 35 bits PA, the* encoding format is same with IO_PGTABLE_QUIRK_ARM_MTK_EXT.**/
- IO_PGTABLE_QUIRK_ARM_TTBR1: (ARM LPAE format) Configure the table
- for use in the upper half of a split address space.
- IO_PGTABLE_QUIRK_ARM_OUTER_WBWA: Override the outer-cacheability
- attributes set in the TCR for a non-coherent page-table walker.
- #define IO_PGTABLE_QUIRK_ARM_NS BIT(0)
- #define IO_PGTABLE_QUIRK_NO_PERMS BIT(1)
- #define IO_PGTABLE_QUIRK_ARM_MTK_EXT BIT(3)
- #define IO_PGTABLE_QUIRK_ARM_TTBR1 BIT(5)
- #define IO_PGTABLE_QUIRK_ARM_OUTER_WBWA BIT(6)
- #define IO_PGTABLE_QUIRK_ARM_NS BIT(0)
- #define IO_PGTABLE_QUIRK_NO_PERMS BIT(1)
- #define IO_PGTABLE_QUIRK_ARM_MTK_EXT BIT(3)
- #define IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT BIT(4)
- #define IO_PGTABLE_QUIRK_ARM_TTBR1 BIT(5)
- #define IO_PGTABLE_QUIRK_ARM_OUTER_WBWA BIT(6) unsigned long quirks; unsigned long pgsize_bitmap; unsigned int ias;
-- 2.18.0