From: Lionel Landwerlin lionel.g.landwerlin@intel.com
The same tests failing on CFL+ platforms are also failing on ICL. Documentation doesn't list the WaAllowPMDepthAndInvocationCountAccessFromUMD workaround for ICL but applying it fixes the same tests as CFL.
v2: Use only one whitelist entry (Lionel)
Signed-off-by: Lionel Landwerlin lionel.g.landwerlin@intel.com Tested-by: Anuj Phogat anuj.phogat@gmail.com Cc: stable@vger.kernel.org Acked-by: Chris Wilson chris@chris-wilson.co.uk Signed-off-by: Chris Wilson chris@chris-wilson.co.uk Link: https://patchwork.freedesktop.org/patch/msgid/20190628120720.21682-4-lionel.... (cherry picked from commit 3fe0107e45ab396342497e06b8924cdd485cde3b) Cc: stable@vger.kernel.org # 6883eab27481: drm/i915: Support flags in whitlist WAs Signed-off-by: Joonas Lahtinen joonas.lahtinen@linux.intel.com --- drivers/gpu/drm/i915/intel_workarounds.c | 13 +++++++++++++ 1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c index bd964fbc667b..5e54de630ef1 100644 --- a/drivers/gpu/drm/i915/intel_workarounds.c +++ b/drivers/gpu/drm/i915/intel_workarounds.c @@ -1075,6 +1075,19 @@ static void icl_whitelist_build(struct i915_wa_list *w)
/* WaEnableStateCacheRedirectToCS:icl */ whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); + + /* + * WaAllowPMDepthAndInvocationCountAccessFromUMD:icl + * + * This covers 4 register which are next to one another : + * - PS_INVOCATION_COUNT + * - PS_INVOCATION_COUNT_UDW + * - PS_DEPTH_COUNT + * - PS_DEPTH_COUNT_UDW + */ + whitelist_reg_ext(w, PS_INVOCATION_COUNT, + RING_FORCE_TO_NONPRIV_RD | + RING_FORCE_TO_NONPRIV_RANGE_4); }
void intel_engine_init_whitelist(struct intel_engine_cs *engine)