From: Honghui Zhang honghui.zhang@mediatek.com
[ Upstream commit c61df57343bf05743f8abbb31eec9a6f05820dd1 ]
Mediatek's HW assigns a MMIO address range (typically starts from 0x20000000 to 0x2fffffff for both mt2712 and mt7622) for PCI usage.
This MMIO address space represents the address space that can be allocated to PCI devices through Base Address Registers.
Even though the full MMIO address range is available to be allocated, it should be enabled by the PCIE_AHB_TRANS_BASE register in the host controller and the size that is enabled is determined by AHB2PCIE_SIZE bits in this register.
Owing to a bug in the MMIO window size computation, current code does not enable the full size of the available MMIO address range in the PCI host controller; if the PCI devices BARs requested size exceeds the size enabled through the PCIE_AHB_TRANS_BASE register the requests targeting the disabled address address space will be blocked by the root complex causing a system error.
Existing code has never run into a system error in production because even half of the enabled MMIO range (128MB) is big enough for typical devices BAR requests (4MB) but the full MMIO address range should be enabled regardless.
Fix the MMIO window size computation by using resource_size(mem) instead of mem->end - mem->start.
Since the MMIO window size for both MT2712 and MT7622 is 0x10000000, this change will update the parameter passed to fls() from 0xfffffff to 0x10000000 and calculate the whole memory mapped IO range size correctly.
Detected through coccinelle semantic patch (and related warning):
scripts/coccinelle/api/resource_size.cocci:
pcie-mediatek.c:720:13-16: WARNING: Suspicious code. resource_size is maybe missing with mem
Signed-off-by: Honghui Zhang honghui.zhang@mediatek.com [lorenzo.pieralisi@arm.com: rewrote the commit log] Signed-off-by: Lorenzo Pieralisi lorenzo.pieralisi@arm.com Signed-off-by: Sasha Levin sashal@kernel.org --- drivers/pci/controller/pcie-mediatek.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c index 55e471c18e8d..c42fe5c4319f 100644 --- a/drivers/pci/controller/pcie-mediatek.c +++ b/drivers/pci/controller/pcie-mediatek.c @@ -654,7 +654,6 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port) struct resource *mem = &pcie->mem; const struct mtk_pcie_soc *soc = port->pcie->soc; u32 val; - size_t size; int err;
/* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */ @@ -706,8 +705,8 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port) mtk_pcie_enable_msi(port);
/* Set AHB to PCIe translation windows */ - size = mem->end - mem->start; - val = lower_32_bits(mem->start) | AHB2PCIE_SIZE(fls(size)); + val = lower_32_bits(mem->start) | + AHB2PCIE_SIZE(fls(resource_size(mem))); writel(val, port->base + PCIE_AHB_TRANS_BASE0_L);
val = upper_32_bits(mem->start);