On Thu, May 18, 2023 at 05:43:51AM +0000, Vasant Hegde wrote:
IOMMU v2 page table supports 4 level (47 bit) or 5 level (56 bit) virtual address space. Current code assumes it can support 64bit IOVA address space. If IOVA allocator allocates virtual address > 47/56 bit (depending on page table level) then it will do wrong mapping and cause invalid translation.
Hence adjust aperture size to use max address supported by the page table.
Reported-by: Jerry Snitselaar jsnitsel@redhat.com Fixes: aaac38f61487 ("iommu/amd: Initial support for AMD IOMMU v2 page table") Cc: Stable@vger.kernel.org # v6.0+ Cc: Suravee Suthikulpanit suravee.suthikulpanit@amd.com Signed-off-by: Vasant Hegde vasant.hegde@amd.com
drivers/iommu/amd/iommu.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-)
Applied for 6.4, thanks Vasant.