This is the start of the stable review cycle for the 4.9.310 release.
There are 43 patches in this series, all will be posted as a response
to this one. If anyone has any issues with these being applied, please
let me know.
Responses should be made by Fri, 08 Apr 2022 18:24:27 +0000.
Anything received after that time might be too late.
The whole patch series can be found in one patch at:
https://www.kernel.org/pub/linux/kernel/v4.x/stable-review/patch-4.9.310-rc…
or in the git tree and branch at:
git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable-rc.git linux-4.9.y
and the diffstat can be found below.
thanks,
greg k-h
-------------
Pseudo-Shortlog of commits:
Greg Kroah-Hartman <gregkh(a)linuxfoundation.org>
Linux 4.9.310-rc1
James Morse <james.morse(a)arm.com>
arm64: Use the clearbhb instruction in mitigations
James Morse <james.morse(a)arm.com>
arm64: add ID_AA64ISAR2_EL1 sys register
James Morse <james.morse(a)arm.com>
KVM: arm64: Allow SMCCC_ARCH_WORKAROUND_3 to be discovered and migrated
James Morse <james.morse(a)arm.com>
arm64: Mitigate spectre style branch history side channels
James Morse <james.morse(a)arm.com>
KVM: arm64: Add templates for BHB mitigation sequences
James Morse <james.morse(a)arm.com>
arm64: Add percpu vectors for EL1
James Morse <james.morse(a)arm.com>
arm64: entry: Add macro for reading symbol addresses from the trampoline
James Morse <james.morse(a)arm.com>
arm64: entry: Add vectors that have the bhb mitigation sequences
James Morse <james.morse(a)arm.com>
arm64: Move arm64_update_smccc_conduit() out of SSBD ifdef
James Morse <james.morse(a)arm.com>
arm64: entry: Add non-kpti __bp_harden_el1_vectors for mitigations
James Morse <james.morse(a)arm.com>
arm64: entry: Allow the trampoline text to occupy multiple pages
James Morse <james.morse(a)arm.com>
arm64: entry: Make the kpti trampoline's kpti sequence optional
James Morse <james.morse(a)arm.com>
arm64: entry: Move trampoline macros out of ifdef'd section
James Morse <james.morse(a)arm.com>
arm64: entry: Don't assume tramp_vectors is the start of the vectors
James Morse <james.morse(a)arm.com>
arm64: entry: Allow tramp_alias to access symbols after the 4K boundary
James Morse <james.morse(a)arm.com>
arm64: entry: Move the trampoline data page before the text page
James Morse <james.morse(a)arm.com>
arm64: entry: Free up another register on kpti's tramp_exit path
James Morse <james.morse(a)arm.com>
arm64: entry: Make the trampoline cleanup optional
James Morse <james.morse(a)arm.com>
arm64: entry.S: Add ventry overflow sanity checks
Suzuki K Poulose <suzuki.poulose(a)arm.com>
arm64: Add helper to decode register from instruction
Anshuman Khandual <anshuman.khandual(a)arm.com>
arm64: Add Cortex-X2 CPU part definition
Suzuki K Poulose <suzuki.poulose(a)arm.com>
arm64: Add Neoverse-N2, Cortex-A710 CPU part definition
Rob Herring <robh(a)kernel.org>
arm64: Add part number for Arm Cortex-A77
Marc Zyngier <marc.zyngier(a)arm.com>
arm64: Add part number for Neoverse N1
Marc Zyngier <marc.zyngier(a)arm.com>
arm64: Make ARM64_ERRATUM_1188873 depend on COMPAT
Marc Zyngier <marc.zyngier(a)arm.com>
arm64: Add silicon-errata.txt entry for ARM erratum 1188873
Arnd Bergmann <arnd(a)arndb.de>
arm64: arch_timer: avoid unused function warning
Marc Zyngier <marc.zyngier(a)arm.com>
arm64: arch_timer: Add workaround for ARM erratum 1188873
Marc Zyngier <marc.zyngier(a)arm.com>
arm64: arch_timer: Add erratum handler for CPU-specific capability
Marc Zyngier <marc.zyngier(a)arm.com>
arm64: arch_timer: Add infrastructure for multiple erratum detection methods
Ding Tianhong <dingtianhong(a)huawei.com>
clocksource/drivers/arm_arch_timer: Introduce generic errata handling infrastructure
Ding Tianhong <dingtianhong(a)huawei.com>
clocksource/drivers/arm_arch_timer: Remove fsl-a008585 parameter
Suzuki K Poulose <suzuki.poulose(a)arm.com>
arm64: capabilities: Add support for checks based on a list of MIDRs
Suzuki K Poulose <suzuki.poulose(a)arm.com>
arm64: Add helpers for checking CPU MIDR against a range
Suzuki K Poulose <suzuki.poulose(a)arm.com>
arm64: capabilities: Clean up midr range helpers
Suzuki K Poulose <suzuki.poulose(a)arm.com>
arm64: capabilities: Add flags to handle the conflicts on late CPU
Suzuki K Poulose <suzuki.poulose(a)arm.com>
arm64: capabilities: Prepare for fine grained capabilities
Suzuki K Poulose <suzuki.poulose(a)arm.com>
arm64: capabilities: Move errata processing code
Suzuki K Poulose <suzuki.poulose(a)arm.com>
arm64: capabilities: Move errata work around check on boot CPU
Dave Martin <dave.martin(a)arm.com>
arm64: capabilities: Update prototype for enable call back
Suzuki K Poulose <suzuki.poulose(a)arm.com>
arm64: Add MIDR encoding for Arm Cortex-A55 and Cortex-A35
James Morse <james.morse(a)arm.com>
arm64: Remove useless UAO IPI and describe how this gets enabled
Robert Richter <rrichter(a)cavium.com>
arm64: errata: Provide macro for major and minor cpu revisions
-------------
Diffstat:
Documentation/arm64/silicon-errata.txt | 1 +
Documentation/kernel-parameters.txt | 9 -
Makefile | 4 +-
arch/arm/include/asm/kvm_host.h | 5 +
arch/arm/kvm/psci.c | 4 +
arch/arm64/Kconfig | 24 ++
arch/arm64/include/asm/arch_timer.h | 44 ++-
arch/arm64/include/asm/assembler.h | 34 ++
arch/arm64/include/asm/cpu.h | 1 +
arch/arm64/include/asm/cpucaps.h | 4 +-
arch/arm64/include/asm/cpufeature.h | 232 ++++++++++++-
arch/arm64/include/asm/cputype.h | 63 ++++
arch/arm64/include/asm/fixmap.h | 6 +-
arch/arm64/include/asm/insn.h | 2 +
arch/arm64/include/asm/kvm_host.h | 4 +
arch/arm64/include/asm/kvm_mmu.h | 2 +-
arch/arm64/include/asm/mmu.h | 8 +-
arch/arm64/include/asm/processor.h | 6 +-
arch/arm64/include/asm/sections.h | 6 +
arch/arm64/include/asm/sysreg.h | 5 +
arch/arm64/include/asm/vectors.h | 74 +++++
arch/arm64/kernel/bpi.S | 55 +++
arch/arm64/kernel/cpu_errata.c | 591 ++++++++++++++++++++++++++-------
arch/arm64/kernel/cpufeature.c | 167 +++++++---
arch/arm64/kernel/cpuinfo.c | 1 +
arch/arm64/kernel/entry.S | 197 ++++++++---
arch/arm64/kernel/fpsimd.c | 1 +
arch/arm64/kernel/insn.c | 29 ++
arch/arm64/kernel/smp.c | 6 -
arch/arm64/kernel/traps.c | 4 +-
arch/arm64/kernel/vmlinux.lds.S | 2 +-
arch/arm64/kvm/hyp/hyp-entry.S | 4 +
arch/arm64/kvm/hyp/switch.c | 9 +-
arch/arm64/mm/fault.c | 17 +-
arch/arm64/mm/mmu.c | 11 +-
drivers/clocksource/Kconfig | 4 +
drivers/clocksource/arm_arch_timer.c | 192 ++++++++---
include/linux/arm-smccc.h | 7 +
38 files changed, 1504 insertions(+), 331 deletions(-)
VAPTCHA
Impossible for bots, easy for humans.
[view?uuid=00e6ede8b6194d688afbd7b8c90ef44c&lang=en]
Dear webmaster:
SMSVAPTCHA is a new human-machine verification solution supported by
artificial intelligence and big data, excelling in accurately
identifying and intercepting various attack requests. Equipped with
efficient and evolving risk control engine, SMSVAPTCHA has outstanding
advantages in security and user experience over traditional
verification codes.
Safer
Unbreakable,impossible for any tricky bots.
Powerful AI&algorithm security strategies.
Easier
User-friendly, it takes only 1s for the user to complete the test.
Online support, easy and quick deployment.
Free
Completely free, there is no QPS or verification limit.
Over 100,000 global webmsters choose SMSVAPTCHA.
[1]Get Started →
This email was sent to webmaster. If you no longer wish to receive
these emails you may
[2]unsubscribe at any time.
References
1. https://00e6e.zzra.com/api/v1/mail/click?uuid=00e6ede8b6194d688afbd7b8c90ef…
2. https://00e6e.zzra.com/api/v1/mail/unsubscribe?uuid=00e6ede8b6194d688afbd7b…
Dear Sir or Madam,
It is our pleasure to learn your company from Google,hoping
our belowed introduction letter would not take much of your time!
We,Chaozhou FTD Ceramic Co.,Ltd,as one of the leading
trading company in sanitary ware.Our core business is to have resources
integration of our local sanitary ware factories and offer our
customers good quality products basd on reasonable price.The reason why
we can compete with factories,survive and grow up is because we have
good resources and our professional QC do 100% on quality control and
make sure that all the products offered by us are within quality
standard,which can minimize the complain from quality.
To learn more about our products,you are welcome to visit
our website any time.
Look forward to hearing from you soon,thank you!
Best regards
Ivan
Chaozhou FTD Ceramic Cooperation Limited
Liya Indu.Zone,Guxiang,Chaozhou,Guangdong,China
Tel: 0086-768-2338905
Fax: 0086-768-2338905
Cell: 0086-186 8805 0197
E-mail: [1]ivan(a)ftdceramic.net
Website: [2]www.ftdceramic.com
References
1. mailto:ivan@ftdceramic.net
2. file:///C:/Users/Administrator/AppData/Roaming/Foxmail7/Temp-5164-202103051…
Dear Sir or Madam,
It is our pleasure to learn your company from Google,hoping
our belowed introduction letter would not take much of your time!
We,Chaozhou FTD Ceramic Co.,Ltd,as one of the leading
trading company in sanitary ware.Our core business is to have resources
integration of our local sanitary ware factories and offer our
customers good quality products basd on reasonable price.The reason why
we can compete with factories,survive and grow up is because we have
good resources and our professional QC do 100% on quality control and
make sure that all the products offered by us are within quality
standard,which can minimize the complain from quality.
To learn more about our products,you are welcome to visit
our website any time.
Look forward to hearing from you soon,thank you!
Best regards
Ivan
Chaozhou FTD Ceramic Cooperation Limited
Liya Indu.Zone,Guxiang,Chaozhou,Guangdong,China
Tel: 0086-768-2338905
Fax: 0086-768-2338905
Cell: 0086-186 8805 0197
E-mail: [1]ivan(a)ftdceramic.net
Website: [2]www.ftdceramic.com
References
1. mailto:ivan@ftdceramic.net
2. file:///C:/Users/Administrator/AppData/Roaming/Foxmail7/Temp-5164-202103051…
perf build errors on i386 [1] on Linux next-20220407 [2]
usdt.c:1181:5: error: "__x86_64__" is not defined, evaluates to 0
[-Werror=undef]
1181 | #if __x86_64__
| ^~~~~~~~~~
usdt.c:1196:5: error: "__x86_64__" is not defined, evaluates to 0
[-Werror=undef]
1196 | #if __x86_64__
| ^~~~~~~~~~
cc1: all warnings being treated as errors
make[4]: *** [/builds/linux/tools/build/Makefile.build:97:
/home/tuxbuild/.cache/tuxmake/builds/1/build/libbpf/staticobjs/usdt.o]
Error 1
make[4]: *** Waiting for unfinished jobs....
CC /home/tuxbuild/.cache/tuxmake/builds/1/build/util/values.o
CC /home/tuxbuild/.cache/tuxmake/builds/1/build/tests/backward-ring-buffer.o
CC /home/tuxbuild/.cache/tuxmake/builds/1/build/tests/sdt.o
CC /home/tuxbuild/.cache/tuxmake/builds/1/build/tests/is_printable_array.o
CC /home/tuxbuild/.cache/tuxmake/builds/1/build/util/debug.o
CC /home/tuxbuild/.cache/tuxmake/builds/1/build/util/fncache.o
CC /home/tuxbuild/.cache/tuxmake/builds/1/build/tests/bitmap.o
CC /home/tuxbuild/.cache/tuxmake/builds/1/build/util/machine.o
libbpf.c: In function 'attach_uprobe':
libbpf.c:10946:50: error: format '%li' expects argument of type 'long
int *', but argument 4 has type 'size_t *' {aka 'unsigned int *'}
[-Werror=format=]
10946 | n = sscanf(func_name, "%m[a-zA-Z0-9_.]+%li", &func, &offset);
| ~~^ ~~~~~~~
| | |
| long int *
size_t * {aka unsigned int *}
| %i
cc1: all warnings being treated as errors
make[4]: *** [/builds/linux/tools/build/Makefile.build:96:
/home/tuxbuild/.cache/tuxmake/builds/1/build/libbpf/staticobjs/libbpf.o]
Error 1
metadata:
git_ref: master
git_repo: https://gitlab.com/Linaro/lkft/mirrors/next/linux-next
git_sha: 2e9a9857569ec27e64d2ddd01294bbe3c736acb1
git_describe: next-20220407
kernel-config: https://builds.tuxbuild.com/27SL0lCnWoPP04Jn8zKQ5nEEX7i/config
target_arch: i386
Reported-by: Linux Kernel Functional Testing <lkft(a)linaro.org>
--
Linaro LKFT
https://lkft.linaro.org
[1] https://builds.tuxbuild.com/27SL0lCnWoPP04Jn8zKQ5nEEX7i/
[2] https://gitlab.com/Linaro/lkft/mirrors/next/linux-next/-/jobs/2302706510