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from ae98859fc1d [Power9]Legalize and emit code for quad-precision convert f [...]
new 99cf6a153e3 [InstCombine] improve code comment; NFC
new 03a0661f606 [Hexagon] Add more lit tests
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Summary of changes:
.../InstCombine/InstCombineMulDivRem.cpp | 4 +-
test/CodeGen/Hexagon/addrmode-align.ll | 61 ++++
.../Hexagon/intrinsics/atomicrmw_bitwise_native.ll | 65 ++++
test/CodeGen/Hexagon/intrinsics/atomicrmw_nand.ll | 56 ++++
.../Hexagon/lsr-post-inc-cross-use-offsets.ll | 352 +++++++++++++++++++++
test/CodeGen/Hexagon/retval-redundant-copy.ll | 20 ++
test/CodeGen/Hexagon/swp-bad-sched.ll | 147 +++++++++
test/CodeGen/Hexagon/swp-const-tc1.ll | 70 ++++
test/CodeGen/Hexagon/swp-epilog-phi7.ll | 275 ++++++++++++++++
test/CodeGen/Hexagon/swp-memrefs-epilog1.ll | 90 ++++++
test/CodeGen/Hexagon/swp-phi-ch-offset.ll | 66 ++++
test/CodeGen/Hexagon/swp-resmii-1.ll | 114 +++++++
test/CodeGen/Hexagon/vdotprod.ll | 51 +++
13 files changed, 1369 insertions(+), 2 deletions(-)
create mode 100644 test/CodeGen/Hexagon/addrmode-align.ll
create mode 100644 test/CodeGen/Hexagon/intrinsics/atomicrmw_bitwise_native.ll
create mode 100644 test/CodeGen/Hexagon/intrinsics/atomicrmw_nand.ll
create mode 100644 test/CodeGen/Hexagon/lsr-post-inc-cross-use-offsets.ll
create mode 100644 test/CodeGen/Hexagon/retval-redundant-copy.ll
create mode 100644 test/CodeGen/Hexagon/swp-bad-sched.ll
create mode 100644 test/CodeGen/Hexagon/swp-const-tc1.ll
create mode 100644 test/CodeGen/Hexagon/swp-epilog-phi7.ll
create mode 100644 test/CodeGen/Hexagon/swp-memrefs-epilog1.ll
create mode 100644 test/CodeGen/Hexagon/swp-phi-ch-offset.ll
create mode 100644 test/CodeGen/Hexagon/swp-resmii-1.ll
create mode 100644 test/CodeGen/Hexagon/vdotprod.ll
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from 6ab4090c4 This is PR36799.
new 76e259262 [ELF] GotSection increment NumEntries when Target saves Globa [...]
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Summary of changes:
ELF/SyntheticSections.cpp | 14 +++++++++++---
test/ELF/ppc64_entry_point.s | 5 ++++-
2 files changed, 15 insertions(+), 4 deletions(-)
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from 4f7ae6f505 Remove struct keyword from section_addr_info
new 0b7a4aa6ba Fix case where IR file provides symbol visibility but replac [...]
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Summary of changes:
gold/ChangeLog | 12 ++++++++
gold/plugin.cc | 3 +-
gold/testsuite/Makefile.am | 21 +++++++++++++
gold/testsuite/Makefile.in | 28 ++++++++++++++++--
.../{ehdr_start_test_4.sh => plugin_pr22868.sh} | 13 ++++++---
...n_test_wrap_symbols_2.cc => plugin_pr22868_a.c} | 17 ++++-------
.../{plugin_test_7_1.c => plugin_pr22868_b.c} | 34 ++++++++++------------
7 files changed, 90 insertions(+), 38 deletions(-)
copy gold/testsuite/{ehdr_start_test_4.sh => plugin_pr22868.sh} (68%)
copy gold/testsuite/{plugin_test_wrap_symbols_2.cc => plugin_pr22868_a.c} (76%)
copy gold/testsuite/{plugin_test_7_1.c => plugin_pr22868_b.c} (57%)
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from 10fe375630c Disable [MachineLICM] Add functions to MachineLICM to hoist [...]
new ba5863e984a [PowerPC] Infrastructure work. Implement getting the opcode [...]
new ae98859fc1d [Power9]Legalize and emit code for quad-precision convert f [...]
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Summary of changes:
lib/Target/PowerPC/PPCISelLowering.cpp | 17 +-
lib/Target/PowerPC/PPCInstr64Bit.td | 225 +++++++-------
lib/Target/PowerPC/PPCInstrAltivec.td | 24 +-
lib/Target/PowerPC/PPCInstrFormats.td | 51 ++-
lib/Target/PowerPC/PPCInstrInfo.cpp | 517 ++++++++++++++++---------------
lib/Target/PowerPC/PPCInstrInfo.h | 29 +-
lib/Target/PowerPC/PPCInstrInfo.td | 170 +++++-----
lib/Target/PowerPC/PPCInstrQPX.td | 38 +--
lib/Target/PowerPC/PPCInstrVSX.td | 77 ++---
test/CodeGen/PowerPC/f128-arith.ll | 30 +-
test/CodeGen/PowerPC/vsxD-Form-spills.ll | 16 +-
11 files changed, 671 insertions(+), 523 deletions(-)
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unknown user pushed a change to branch master
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from 1061d9685 Fix TestDisassembleBreakpoint broken by r328488
new 4b91a943a Fix check for verbose logging.
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.../LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCRuntimeV2.cpp | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
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from 5cd3e386e0 Make gdbserver reg_defs a vector of objects
new 4f7ae6f505 Remove struct keyword from section_addr_info
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gdb/ChangeLog | 7 +++++++
gdb/symfile.c | 2 +-
gdb/windows-nat.c | 2 +-
3 files changed, 9 insertions(+), 2 deletions(-)
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from e67cab7ed99 [Pipeliner] Several node-ordering fixes
new 10fe375630c Disable [MachineLICM] Add functions to MachineLICM to hoist [...]
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lib/CodeGen/MachineLICM.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
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from 42e9b96ddfd Remove an unneeded (& mislayered) include from Target/Targe [...]
new b22cddf04e5 [Pipeliner] Check for affine expression in isLoopCarriedOrder
new 92d40b0a3d4 [X86][Btver2] Add CVTSI2SD/CVTSI2SS scheduler costs
new 476b2588b14 [AMDGPU] Improve disassembler error handling
new e67cab7ed99 [Pipeliner] Several node-ordering fixes
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Summary of changes:
lib/CodeGen/MachinePipeliner.cpp | 48 ++++++++++++---------
.../AMDGPU/Disassembler/AMDGPUDisassembler.cpp | 5 ++-
lib/Target/X86/X86ScheduleBtVer2.td | 21 ++++++++--
test/CodeGen/X86/sse-schedule.ll | 16 +++----
test/CodeGen/X86/sse2-schedule.ll | 16 +++----
test/MC/AMDGPU/data.s | 27 ++++++++++++
test/tools/llvm-mca/X86/BtVer2/resources-sse1.s | 8 ++--
tools/llvm-objdump/llvm-objdump.cpp | 49 +++++++++++++++-------
8 files changed, 130 insertions(+), 60 deletions(-)
create mode 100644 test/MC/AMDGPU/data.s
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from 1fc609130a [OPENMP] Codegen for declare target with link clause.
new b303637398 [CodeGen] Mark fma as const for Android
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lib/Sema/SemaDecl.cpp | 4 ++--
test/CodeGen/math-builtins.c | 6 ++++++
2 files changed, 8 insertions(+), 2 deletions(-)
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from b9e7253e391 [SLP] Add a test case. NFC.
new b709662b9c2 [Pipeliner] Add missing loop carried dependences
new fecaf52c6b1 Remove unneeded (& mislayered) include from TargetMachine.c [...]
new 42e9b96ddfd Remove an unneeded (& mislayered) include from Target/Targe [...]
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Summary of changes:
lib/CodeGen/MachinePipeliner.cpp | 37 ++++++++++------
lib/Target/TargetLoweringObjectFile.cpp | 1 -
lib/Target/TargetMachine.cpp | 1 -
test/CodeGen/Hexagon/swp-loop-carried-unknown.ll | 54 ++++++++++++++++++++++++
4 files changed, 77 insertions(+), 16 deletions(-)
create mode 100644 test/CodeGen/Hexagon/swp-loop-carried-unknown.ll
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