Tcwg-commits January 2020

tcwg-commits@lists.linaro.org

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12654 discussions

[gcc] branch master updated (a6b8833f34a -> 69ffead97a2)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from a6b8833f34a Fix amdgcn issue with '0' constraints new fb9c849560f Check mask argument's type when vectorising conditional functions new 69ffead97a2 Require equal shift amounts for IFN_DIV_POW2 The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/ChangeLog | 13 ++++++++ gcc/testsuite/ChangeLog | 11 +++++++ gcc/testsuite/gcc.dg/vect/vect-cond-arith-8.c | 8 +++++ gcc/testsuite/gcc.target/aarch64/sve/asrdiv_1.c | 8 ++--- gcc/testsuite/gcc.target/aarch64/sve/asrdiv_2.c | 19 ++++++++++++ gcc/testsuite/gcc.target/aarch64/sve/asrdiv_3.c | 19 ++++++++++++ gcc/testsuite/gcc.target/aarch64/sve/cond_fmul_5.c | 9 ++++++ gcc/tree-vect-slp.c | 30 +++++++++++++------ gcc/tree-vect-stmts.c | 35 ++++++++++------------ 9 files changed, 120 insertions(+), 32 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/vect/vect-cond-arith-8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/asrdiv_2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/asrdiv_3.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fmul_5.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 8 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-defconfig updated (6a6e6f04ec2 -> 3abc2927cb2)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-defconfig in repository toolchain/ci/llvm-project. from 6a6e6f04ec2 [X86] Move combineLogicBlendIntoConditionalNegate before co [...] adds e3bd0118903 [X86][SSE] Combine combineLogicBlendIntoConditionalNegate f [...] adds c764304adc5 [MC] Drop an unused rule about absolute temporary symbols adds 124b918bd34 [MC] Merge MCSymbol::getSectionPtr into getSection and simplify adds 47115123843 Fix oversight in AST traversal helper adds ad0a45833b9 Allow using traverse() with bindings adds 586acd84902 [MC] Delete MCSection::{rbegin,rend} adds b18cb9c4716 [Gnu toolchain] Look at standard GCC paths for libstdcxx by [...] adds 35efef5351e Add missing test adds 5511861e6dc [MC][ARM] Delete MCSection::HasData and move SHF_ARM_PURECO [...] adds 445f4d2310e Clang-format previous commit adds 83a9321f60d [Coroutines] Remove corresponding phi values when apply sim [...] adds ca3bf289a7f [NFC] Modify the format: Drop the else since we alerady ret [...] adds 95840866b7d [X86] Improve v2i64->v2f32 and v4i64->v4f32 uint_to_fp on a [...] adds 2c053109fa8 [MC] Delete MCFragment::isDummy. NFC adds b9780f4f80b [DAGCombine] Don't check the legality of type when combine [...] adds 806a2b1f3d8 [MC] Reorder MCFragment members to decrease padding adds 2e466950031 [MC] Reorder members of MCFragment's subclasses to decrease [...] adds 8aae6455c07 [mlir][spirv] Update SPIR-V documentation with information [...] adds 19ace449a3d [TargetLowering] Use SETCC input type to call getBooleanCon [...] adds ce67db41853 [Clang] Force rtlib=platform in test to avoid fails with CL [...] adds a7929533300 [Metadata] Add TBAA struct metadata to `AAMDNode` adds c5fb73c5d1b [APFloat] Add recoverable string parsing errors to APFloat adds 103a58c8f2b Add ExternalAAWrapperPass to createLegacyPMAAResults. adds aab72f89b19 [mlir] Update mlir/CMakeLists.txt to install *.def files adds f3f7dc3d299 [APFloat] Fix compilation warnings adds 5173bfcbc48 Add interface emitPrefix for MCCodeEmitter adds 0efc9e5a8cc [ARM][MVE] More MVETailPredication debug messages. NFC. adds 7180d9568df Fix MSVC "not all control paths return a value" warning. NFCI. adds d68904f957a [NFC] Fix trivial typos in comments adds 89b11843254 [test][DebugInfo][NFC] Rename method for clarity adds 6fa6000e3e2 [DAG] DAGCombiner::XformToShuffleWithZero - use APInt::extr [...] adds 5d986a68a59 [CostModel][X86] Add missing scalar i64->f32 uitofp costs adds de735247c8b [X86] Add extra PR43971 test case mentioned in D70267 adds d45aafa2fbc [clang-format] fix conflict between FormatStyle::BWACS_Mult [...] adds d67c4cc2eb4 [mlir][Linalg] Reimplement and extend getStridesAndOffset adds f1c85ecdfcc AMDGPU/GlobalISel: Select more G_EXTRACTs correctly adds bc763c42bbc [lldb] [Process/NetBSD] Remove unused orig_*ax use adds e4464bf3d45 AMDGPU/GlobalISel: Select scalar v2s16 G_BUILD_VECTOR adds b99ef32d041 [ARM,MVE] Generate the right instruction for vmaxnmq_m_f16. adds 4978296cd8e [ARM,MVE] Support -ve offsets in gather-load intrinsics. adds 34817e04fee [ARM,MVE] Fix many signedness errors in MVE intrinsics. adds ea5abf14530 Fix "use of uninitialized variable" static analyzer warning. NFCI. adds 5bcc747393b Fix "use of uninitialized variable" static analyzer warning [...] adds ea2c159f966 [AMDGPU] Fix "use of uninitialized variable" static analyze [...] adds 1d549cff48c [NFC] Fixes -Wrange-loop-analysis warnings adds eec0240f971 Adds -Wrange-loop-analysis to -Wall adds 61b5e727b7c [AIX] Use csect reference for function address constants adds 0eb981b8ce7 [ARM] Use correct TRAP opcode for thumb in FastISel adds f88d52728b9 [ARM] Use the correct opcodes for Thumb2 segmented stack fr [...] adds 3e1f3b164cc [llvm-libc] Fix missing virtual destructor adds 83ec9b51ed2 [AIX] Use csect reference for function address constants new b3757f3091d [lldb/CMake] Autodetect Python dependency new 8eba3fbb12f [lldb/Test] Temporarily skip TestFoundationDisassembly on t [...] new 350da402ef6 [clang-tidy] new check: bugprone-signed-char-misuse new ba4ca37b814 [gn build] Port 350da402ef6 new 896b84ac2c7 [llvm-readelf] Print EI_ABIVERSION as decimal instead of he [...] new 3abc2927cb2 [lldb/Test] Move @skipIfAsan from test class to test methods. The 6 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: .../clang-tidy/bugprone/BugproneTidyModule.cpp | 3 + .../clang-tidy/bugprone/CMakeLists.txt | 1 + .../clang-tidy/bugprone/SignedCharMisuseCheck.cpp | 104 ++++ .../clang-tidy/bugprone/SignedCharMisuseCheck.h | 44 ++ .../clang-tidy/readability/MagicNumbersCheck.cpp | 8 +- .../clang-tidy/utils/FixItHintUtils.cpp | 1 + clang-tools-extra/docs/ReleaseNotes.rst | 6 + .../checks/bugprone-signed-char-misuse.rst | 76 +++ clang-tools-extra/docs/clang-tidy/checks/list.rst | 1 + .../bugprone-signed-char-misuse-fsigned-char.cpp | 9 + .../bugprone-signed-char-misuse-funsigned-char.cpp | 17 + .../bugprone-signed-char-misuse-with-option.cpp | 74 +++ .../checkers/bugprone-signed-char-misuse.cpp | 123 ++++ clang/include/clang/ASTMatchers/ASTMatchers.h | 11 + clang/include/clang/Basic/DiagnosticGroups.td | 2 +- clang/include/clang/Basic/arm_mve.td | 75 ++- clang/include/clang/Basic/arm_mve_defs.td | 5 +- clang/lib/AST/Expr.cpp | 2 +- clang/lib/ASTMatchers/ASTMatchersInternal.cpp | 5 + clang/lib/Driver/ToolChains/Gnu.cpp | 104 +++- clang/lib/Driver/ToolChains/Gnu.h | 9 + clang/lib/Driver/ToolChains/Hurd.cpp | 6 +- clang/lib/Driver/ToolChains/Hurd.h | 4 + clang/lib/Driver/ToolChains/Linux.cpp | 77 +-- clang/lib/Driver/ToolChains/Linux.h | 7 +- clang/lib/Format/UnwrappedLineFormatter.cpp | 13 + clang/lib/Lex/LiteralSupport.cpp | 8 +- .../CodeGen/arm-mve-intrinsics/scatter-gather.c | 60 +- clang/test/CodeGen/arm-mve-intrinsics/vabdq.c | 18 +- clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c | 18 +- clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c | 12 +- clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c | 8 +- clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c | 18 +- clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c | 8 +- clang/test/CodeGen/arm-mve-intrinsics/vminq.c | 14 +- clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c | 18 +- clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c | 24 +- clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c | 18 +- clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c | 6 +- clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c | 6 +- clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c | 20 +- clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c | 18 +- clang/test/Driver/cross-linux.c | 3 + clang/test/Misc/warning-wall.c | 4 +- clang/test/Sema/arm-mve-immediates.c | 28 +- clang/test/SemaCXX/warn-range-loop-analysis.cpp | 1 + .../ASTMatchers/ASTMatchersTraversalTest.cpp | 32 + clang/unittests/Format/FormatTest.cpp | 37 +- clang/utils/TableGen/MveEmitter.cpp | 11 +- libc/utils/HdrGen/CMakeLists.txt | 1 + libc/utils/HdrGen/Command.cpp | 15 + libc/utils/HdrGen/Command.h | 2 + lld/test/ELF/mips-n32-rels.s | 2 +- lldb/cmake/modules/FindPythonInterpAndLibs.cmake | 51 ++ lldb/cmake/modules/LLDBConfig.cmake | 53 +- .../cmake/modules/FindPythonInterpAndLibs.cmake | 51 ++ .../objc/foundation/TestFoundationDisassembly.py | 2 + .../NetBSD/NativeRegisterContextNetBSD_x86_64.cpp | 5 - llvm/bindings/ocaml/llvm/llvm.mli | 2 +- llvm/include/llvm/ADT/APFloat.h | 11 +- llvm/include/llvm/ADT/PointerUnion.h | 2 +- llvm/include/llvm/Analysis/ValueTracking.h | 4 +- .../include/llvm/CodeGen/GlobalISel/CallLowering.h | 2 +- llvm/include/llvm/DebugInfo/GSYM/FunctionInfo.h | 2 +- llvm/include/llvm/DebugInfo/GSYM/GsymCreator.h | 6 +- .../llvm/ExecutionEngine/Orc/OrcABISupport.h | 2 +- llvm/include/llvm/IR/InstrTypes.h | 2 +- llvm/include/llvm/IR/IntrinsicsARM.td | 61 +- llvm/include/llvm/IR/Metadata.h | 28 +- llvm/include/llvm/MC/MCCodeEmitter.h | 6 + llvm/include/llvm/MC/MCFragment.h | 92 +-- llvm/include/llvm/MC/MCSection.h | 13 - llvm/include/llvm/MC/MCSymbol.h | 10 +- llvm/include/llvm/Support/Allocator.h | 2 +- .../llvm/Target/GlobalISel/SelectionDAGCompat.td | 1 + llvm/include/llvm/Target/Target.td | 2 +- llvm/include/llvm/Transforms/IPO/Attributor.h | 6 +- llvm/lib/Analysis/AliasAnalysis.cpp | 5 + llvm/lib/Analysis/TypeBasedAliasAnalysis.cpp | 17 +- llvm/lib/Bitcode/Reader/MetadataLoader.cpp | 2 +- llvm/lib/CodeGen/Analysis.cpp | 2 +- llvm/lib/CodeGen/LiveDebugVariables.cpp | 2 +- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 17 +- .../CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp | 2 +- .../CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 2 +- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 2 +- llvm/lib/CodeGen/TwoAddressInstructionPass.cpp | 2 +- llvm/lib/DebugInfo/DWARF/DWARFDebugLine.cpp | 2 +- llvm/lib/IR/Metadata.cpp | 1 + llvm/lib/MC/MCAssembler.cpp | 14 +- llvm/lib/MC/MCExpr.cpp | 2 +- llvm/lib/MC/MCFragment.cpp | 6 +- llvm/lib/MC/MCObjectStreamer.cpp | 6 - llvm/lib/MC/MCParser/AsmParser.cpp | 3 +- llvm/lib/MC/MCParser/COFFAsmParser.cpp | 2 +- llvm/lib/MC/MCSection.cpp | 3 +- llvm/lib/ProfileData/GCOV.cpp | 2 +- llvm/lib/Support/APFloat.cpp | 155 +++-- llvm/lib/Support/StringRef.cpp | 10 +- llvm/lib/Target/AArch64/AArch64CallLowering.cpp | 2 +- llvm/lib/Target/AArch64/AArch64RegisterInfo.td | 2 +- .../Target/AArch64/AsmParser/AArch64AsmParser.cpp | 14 +- llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp | 2 +- .../Target/AMDGPU/AMDGPUInstructionSelector.cpp | 26 +- llvm/lib/Target/AMDGPU/AMDGPUInstructions.td | 22 +- .../Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 4 +- .../AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp | 1 + llvm/lib/Target/AMDGPU/R600AsmPrinter.cpp | 2 +- llvm/lib/Target/AMDGPU/SIInstructions.td | 41 +- llvm/lib/Target/ARM/ARMCallingConv.cpp | 2 +- llvm/lib/Target/ARM/ARMFastISel.cpp | 8 +- llvm/lib/Target/ARM/ARMFrameLowering.cpp | 6 +- llvm/lib/Target/ARM/ARMISelLowering.cpp | 2 +- llvm/lib/Target/ARM/ARMInstrMVE.td | 81 ++- llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp | 4 + llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 2 +- .../Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp | 7 +- .../lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.cpp | 2 +- llvm/lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.h | 2 +- llvm/lib/Target/ARM/MVETailPredication.cpp | 157 +++-- llvm/lib/Target/Hexagon/HexagonRegisterInfo.td | 2 +- llvm/lib/Target/Mips/MipsInstrFPU.td | 2 +- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp | 22 + llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp | 2 +- .../Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp | 222 ++++--- llvm/lib/Target/X86/X86ISelLowering.cpp | 167 ++++- llvm/lib/Target/X86/X86InstrAVX512.td | 2 +- llvm/lib/Target/X86/X86MCInstLower.cpp | 2 + llvm/lib/Target/X86/X86TargetTransformInfo.cpp | 4 + llvm/lib/Transforms/Coroutines/CoroSplit.cpp | 14 +- llvm/lib/Transforms/IPO/Attributor.cpp | 6 +- llvm/lib/Transforms/IPO/PartialInlining.cpp | 2 +- llvm/lib/Transforms/Utils/AddDiscriminators.cpp | 2 +- llvm/test/Analysis/CostModel/X86/uitofp.ll | 22 +- .../GlobalISel/inst-select-build-vector.v2s16.mir | 239 +++++++ .../AMDGPU/GlobalISel/inst-select-extract.mir | 20 + .../CodeGen/ARM/load_store_opt_clobber_cpsr.mir | 2 +- .../PowerPC/aix-reference-func-addr-const.ll | 32 + llvm/test/CodeGen/PowerPC/sext-vector-inreg.ll | 5 +- .../Thumb2/mve-intrinsics/scatter-gather.ll | 48 +- llvm/test/CodeGen/Thumb2/mve-intrinsics/vabdq.ll | 42 +- llvm/test/CodeGen/Thumb2/mve-intrinsics/vhaddq.ll | 40 +- llvm/test/CodeGen/Thumb2/mve-intrinsics/vhsubq.ll | 30 +- llvm/test/CodeGen/Thumb2/mve-intrinsics/vmaxnmq.ll | 16 +- llvm/test/CodeGen/Thumb2/mve-intrinsics/vmaxq.ll | 26 +- llvm/test/CodeGen/Thumb2/mve-intrinsics/vminnmq.ll | 16 +- llvm/test/CodeGen/Thumb2/mve-intrinsics/vminq.ll | 22 +- llvm/test/CodeGen/Thumb2/mve-intrinsics/vmulhq.ll | 40 +- llvm/test/CodeGen/Thumb2/mve-intrinsics/vmullbq.ll | 40 +- llvm/test/CodeGen/Thumb2/mve-intrinsics/vmulltq.ll | 40 +- llvm/test/CodeGen/Thumb2/mve-intrinsics/vqaddq.ll | 14 +- llvm/test/CodeGen/Thumb2/mve-intrinsics/vqsubq.ll | 14 +- llvm/test/CodeGen/Thumb2/mve-intrinsics/vrhaddq.ll | 42 +- llvm/test/CodeGen/Thumb2/mve-intrinsics/vrmulhq.ll | 40 +- llvm/test/CodeGen/Thumb2/segmented-stacks.ll | 86 ++- .../CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll | 2 +- .../CodeGen/X86/DynamicCalleeSavedRegisters.ll | 2 +- llvm/test/CodeGen/X86/combine-sdiv.ll | 203 +++--- llvm/test/CodeGen/X86/extractelement-load.ll | 45 ++ llvm/test/CodeGen/X86/lea.ll | 2 +- llvm/test/CodeGen/X86/masked_gather_scatter.ll | 2 +- llvm/test/CodeGen/X86/swifterror.ll | 2 +- llvm/test/CodeGen/X86/vec-strict-inttofp-128.ll | 41 +- llvm/test/CodeGen/X86/vec-strict-inttofp-256.ll | 150 ++--- llvm/test/CodeGen/X86/vec_int_to_fp.ll | 690 +++++++++------------ llvm/test/CodeGen/X86/vector-blend.ll | 38 +- .../X86/vector-constrained-fp-intrinsics.ll | 122 ++-- llvm/test/LTO/X86/parallel.ll | 2 +- llvm/test/MC/AArch64/arm64-directive_loh.s | 4 +- llvm/test/MC/ARM/misaligned-blx.s | 2 +- .../Transforms/Coroutines/coro-split-musttail.ll | 27 +- .../Transforms/Coroutines/coro-split-musttail1.ll | 104 ++++ .../test/Transforms/DeadArgElim/naked_functions.ll | 2 +- llvm/test/Transforms/SCCP/apint-basictest3.ll | 2 +- llvm/test/Transforms/SLPVectorizer/X86/align.ll | 2 +- llvm/test/Transforms/SROA/tbaa-struct.ll | 2 +- llvm/test/tools/llvm-objcopy/ELF/partitions.test | 6 +- .../llvm-readobj/ELF/file-header-abi-version.test | 6 +- .../tools/llvm-readobj/ELF/gnu-file-headers.test | 6 +- llvm/tools/llvm-c-test/echo.cpp | 4 +- llvm/tools/llvm-objdump/MachODump.cpp | 2 +- llvm/tools/llvm-readobj/ELFDumper.cpp | 4 +- llvm/unittests/ADT/APFloatTest.cpp | 278 ++++----- llvm/unittests/Analysis/VectorFunctionABITest.cpp | 2 +- llvm/unittests/Analysis/VectorUtilsTest.cpp | 2 +- .../DebugInfo/DWARF/DWARFDebugLineTest.cpp | 38 +- .../WebAssembly/WebAssemblyExceptionInfoTest.cpp | 2 +- llvm/utils/TableGen/CodeGenTarget.cpp | 4 +- llvm/utils/TableGen/CodeGenTarget.h | 4 +- llvm/utils/bugpoint/RemoteRunSafely.sh | 2 +- .../clang-tools-extra/clang-tidy/bugprone/BUILD.gn | 1 + mlir/CMakeLists.txt | 1 + mlir/docs/Dialects/SPIR-V.md | 119 +++- mlir/lib/Dialect/Linalg/Utils/Utils.cpp | 2 +- mlir/lib/IR/StandardTypes.cpp | 246 ++++---- mlir/test/AffineOps/memref-stride-calculation.mlir | 10 + polly/lib/Analysis/ScopGraphPrinter.cpp | 2 +- 197 files changed, 3536 insertions(+), 2237 deletions(-) create mode 100644 clang-tools-extra/clang-tidy/bugprone/SignedCharMisuseCheck.cpp create mode 100644 clang-tools-extra/clang-tidy/bugprone/SignedCharMisuseCheck.h create mode 100644 clang-tools-extra/docs/clang-tidy/checks/bugprone-signed-char-m [...] create mode 100644 clang-tools-extra/test/clang-tidy/checkers/bugprone-signed-char [...] create mode 100644 clang-tools-extra/test/clang-tidy/checkers/bugprone-signed-char [...] create mode 100644 clang-tools-extra/test/clang-tidy/checkers/bugprone-signed-char [...] create mode 100644 clang-tools-extra/test/clang-tidy/checkers/bugprone-signed-char [...] create mode 100644 libc/utils/HdrGen/Command.cpp create mode 100644 lldb/cmake/modules/FindPythonInterpAndLibs.cmake create mode 100644 lldb/lldb/cmake/modules/FindPythonInterpAndLibs.cmake create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector.v2s16.mir create mode 100644 llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll create mode 100644 llvm/test/Transforms/Coroutines/coro-split-musttail1.ll -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 8 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-defconfig updated (cd4bf33 -> a560bfa)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-defconfig in repository toolchain/ci/base-artifacts. discards cd4bf33 0: update: llvm-linux: boot new a560bfa 0: update: llvm-linux: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (cd4bf33) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-arm-s [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 220 +- 02-build_llvm/console.log | 12532 +++++++++++++-------------- 03-build_linux/console.log | 4488 +++++----- 04-boot_linux/console.log | 472 +- 05-check_regression/console.log | 10 +- console.log | 17722 +++++++++++++++++++------------------- jenkins/manifest.sh | 8 +- 7 files changed, 17726 insertions(+), 17726 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 8 months

[toolchain/ci/linux] branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-mainline-defconfig updated (36487907f341 -> c79f46a28239)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-mainline-defconfig in repository toolchain/ci/linux. from 36487907f341 Merge branch 'akpm' (patches from Andrew) adds ac51e005fe14 riscv: mm: use __pa_symbol for kernel symbols adds 0da310e82d3a riscv: gcov: enable gcov for RISC-V adds cfda8617e22a riscv: dts: Add DT support for SiFive L2 cache controller adds 1d8f65798240 riscv: ftrace: correct the condition logic in function gra [...] adds 9d05c18e8d7d clocksource: riscv: add notrace to riscv_sched_clock adds 2f3035da4019 riscv: prefix IRQ_ macro names with an RV_ namespace adds 0e194d9da198 Documentation: riscv: add patch acceptance guidelines adds 768fc661d125 Merge tag 'riscv/for-v5.5-rc5' of git://git.kernel.org/pub [...] adds c79f46a28239 Linux 5.5-rc5 No new revisions were added by this update. Summary of changes: .../debug/gcov-profile-all/arch-support.txt | 2 +- Documentation/process/index.rst | 1 + Documentation/riscv/index.rst | 1 + Documentation/riscv/patch-acceptance.rst | 35 ++++++++++++++++++++++ MAINTAINERS | 1 + Makefile | 2 +- arch/riscv/Kconfig | 1 + arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 15 ++++++++++ arch/riscv/include/asm/csr.h | 18 +++++------ arch/riscv/kernel/ftrace.c | 2 +- arch/riscv/kernel/irq.c | 6 ++-- arch/riscv/mm/init.c | 12 ++++---- drivers/clocksource/timer-riscv.c | 2 +- drivers/irqchip/irq-sifive-plic.c | 2 +- 14 files changed, 77 insertions(+), 23 deletions(-) create mode 100644 Documentation/riscv/patch-acceptance.rst -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 8 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-mainline-defconfig updated (6c67fb0 -> a8937cb)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-mainline-defconfig in repository toolchain/ci/base-artifacts. discards 6c67fb0 0: update: llvm-linux: boot new a8937cb 0: update: llvm-linux: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (6c67fb0) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-release-aarc [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 220 +- 02-build_llvm/console.log | 11872 +++++++++++++++++----------------- 03-build_linux/console.log | 676 +- 04-boot_linux/console.log | 442 +- 05-check_regression/console.log | 10 +- console.log | 13220 +++++++++++++++++++------------------- jenkins/manifest.sh | 8 +- 7 files changed, 13224 insertions(+), 13224 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 8 months

[toolchain/ci/linux] branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-mainline-allnoconfig updated (36487907f341 -> c79f46a28239)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-mainline-allnoconfig in repository toolchain/ci/linux. from 36487907f341 Merge branch 'akpm' (patches from Andrew) adds ac51e005fe14 riscv: mm: use __pa_symbol for kernel symbols adds 0da310e82d3a riscv: gcov: enable gcov for RISC-V adds cfda8617e22a riscv: dts: Add DT support for SiFive L2 cache controller adds 1d8f65798240 riscv: ftrace: correct the condition logic in function gra [...] adds 9d05c18e8d7d clocksource: riscv: add notrace to riscv_sched_clock adds 2f3035da4019 riscv: prefix IRQ_ macro names with an RV_ namespace adds 0e194d9da198 Documentation: riscv: add patch acceptance guidelines adds 768fc661d125 Merge tag 'riscv/for-v5.5-rc5' of git://git.kernel.org/pub [...] adds c79f46a28239 Linux 5.5-rc5 No new revisions were added by this update. Summary of changes: .../debug/gcov-profile-all/arch-support.txt | 2 +- Documentation/process/index.rst | 1 + Documentation/riscv/index.rst | 1 + Documentation/riscv/patch-acceptance.rst | 35 ++++++++++++++++++++++ MAINTAINERS | 1 + Makefile | 2 +- arch/riscv/Kconfig | 1 + arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 15 ++++++++++ arch/riscv/include/asm/csr.h | 18 +++++------ arch/riscv/kernel/ftrace.c | 2 +- arch/riscv/kernel/irq.c | 6 ++-- arch/riscv/mm/init.c | 12 ++++---- drivers/clocksource/timer-riscv.c | 2 +- drivers/irqchip/irq-sifive-plic.c | 2 +- 14 files changed, 77 insertions(+), 23 deletions(-) create mode 100644 Documentation/riscv/patch-acceptance.rst -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 8 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-mainline-allnoconfig updated (ce3f275 -> c7e015e)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-mainline-allnoconfig in repository toolchain/ci/base-artifacts. discards ce3f275 0: update: llvm-linux: boot new c7e015e 0: update: llvm-linux: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (ce3f275) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-release-aarc [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 220 +- 02-build_llvm/console.log | 12064 +++++++++++++++++------------------ 03-build_linux/console.log | 674 +- 05-check_regression/console.log | 10 +- 06-update_baseline/console.log | 10 +- console.log | 12978 +++++++++++++++++++------------------- jenkins/manifest.sh | 8 +- 7 files changed, 12982 insertions(+), 12982 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 8 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-stable-allnoconfig updated (d070e948237 -> 0b0383fab94)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-stable-allnoconfig in repository toolchain/ci/gcc. from d070e948237 Daily bump. adds 0b0383fab94 Daily bump. No new revisions were added by this update. Summary of changes: gcc/DATESTAMP | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 8 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-stable-allnoconfig updated (cfb3377 -> 5c1b9f5)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-stable-allnoconfig in repository toolchain/ci/base-artifacts. discards cfb3377 0: update: binutils-gcc-linux: boot new 5c1b9f5 0: update: binutils-gcc-linux: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (cfb3377) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-release-aarch [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 48 +- 02-prepare_abe/console.log | 422 +- 03-build_abe-binutils/console.log | 11168 +++++++-------- 04-build_abe-stage1/console.log | 13840 +++++++++---------- 05-build_linux/console.log | 798 +- 06-boot_linux/console.log | 4 +- 07-check_regression/console.log | 2 +- 08-update_baseline/console.log | 2 +- console.log | 26284 ++++++++++++++++++------------------ jenkins/manifest.sh | 8 +- 10 files changed, 26292 insertions(+), 26284 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 8 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-allmodconfig updated (3db84f142af -> 83ec9b51ed2)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-allmodconfig in repository toolchain/ci/llvm-project. from 3db84f142af [X86] Merge (identical) LowerGC_TRANSITION_START and LowerG [...] adds 6a6e6f04ec2 [X86] Move combineLogicBlendIntoConditionalNegate before co [...] adds e3bd0118903 [X86][SSE] Combine combineLogicBlendIntoConditionalNegate f [...] adds c764304adc5 [MC] Drop an unused rule about absolute temporary symbols adds 124b918bd34 [MC] Merge MCSymbol::getSectionPtr into getSection and simplify adds 47115123843 Fix oversight in AST traversal helper adds ad0a45833b9 Allow using traverse() with bindings adds 586acd84902 [MC] Delete MCSection::{rbegin,rend} adds b18cb9c4716 [Gnu toolchain] Look at standard GCC paths for libstdcxx by [...] adds 35efef5351e Add missing test adds 5511861e6dc [MC][ARM] Delete MCSection::HasData and move SHF_ARM_PURECO [...] adds 445f4d2310e Clang-format previous commit adds 83a9321f60d [Coroutines] Remove corresponding phi values when apply sim [...] adds ca3bf289a7f [NFC] Modify the format: Drop the else since we alerady ret [...] adds 95840866b7d [X86] Improve v2i64->v2f32 and v4i64->v4f32 uint_to_fp on a [...] adds 2c053109fa8 [MC] Delete MCFragment::isDummy. NFC adds b9780f4f80b [DAGCombine] Don't check the legality of type when combine [...] adds 806a2b1f3d8 [MC] Reorder MCFragment members to decrease padding adds 2e466950031 [MC] Reorder members of MCFragment's subclasses to decrease [...] adds 8aae6455c07 [mlir][spirv] Update SPIR-V documentation with information [...] adds 19ace449a3d [TargetLowering] Use SETCC input type to call getBooleanCon [...] adds ce67db41853 [Clang] Force rtlib=platform in test to avoid fails with CL [...] adds a7929533300 [Metadata] Add TBAA struct metadata to `AAMDNode` adds c5fb73c5d1b [APFloat] Add recoverable string parsing errors to APFloat adds 103a58c8f2b Add ExternalAAWrapperPass to createLegacyPMAAResults. adds aab72f89b19 [mlir] Update mlir/CMakeLists.txt to install *.def files adds f3f7dc3d299 [APFloat] Fix compilation warnings adds 5173bfcbc48 Add interface emitPrefix for MCCodeEmitter adds 0efc9e5a8cc [ARM][MVE] More MVETailPredication debug messages. NFC. adds 7180d9568df Fix MSVC "not all control paths return a value" warning. NFCI. adds d68904f957a [NFC] Fix trivial typos in comments adds 89b11843254 [test][DebugInfo][NFC] Rename method for clarity adds 6fa6000e3e2 [DAG] DAGCombiner::XformToShuffleWithZero - use APInt::extr [...] adds 5d986a68a59 [CostModel][X86] Add missing scalar i64->f32 uitofp costs adds de735247c8b [X86] Add extra PR43971 test case mentioned in D70267 adds d45aafa2fbc [clang-format] fix conflict between FormatStyle::BWACS_Mult [...] adds d67c4cc2eb4 [mlir][Linalg] Reimplement and extend getStridesAndOffset adds f1c85ecdfcc AMDGPU/GlobalISel: Select more G_EXTRACTs correctly adds bc763c42bbc [lldb] [Process/NetBSD] Remove unused orig_*ax use adds e4464bf3d45 AMDGPU/GlobalISel: Select scalar v2s16 G_BUILD_VECTOR new b99ef32d041 [ARM,MVE] Generate the right instruction for vmaxnmq_m_f16. new 4978296cd8e [ARM,MVE] Support -ve offsets in gather-load intrinsics. new 34817e04fee [ARM,MVE] Fix many signedness errors in MVE intrinsics. new ea5abf14530 Fix "use of uninitialized variable" static analyzer warning. NFCI. new 5bcc747393b Fix "use of uninitialized variable" static analyzer warning [...] new ea2c159f966 [AMDGPU] Fix "use of uninitialized variable" static analyze [...] new 1d549cff48c [NFC] Fixes -Wrange-loop-analysis warnings new eec0240f971 Adds -Wrange-loop-analysis to -Wall new 61b5e727b7c [AIX] Use csect reference for function address constants new 0eb981b8ce7 [ARM] Use correct TRAP opcode for thumb in FastISel new f88d52728b9 [ARM] Use the correct opcodes for Thumb2 segmented stack fr [...] new 3e1f3b164cc [llvm-libc] Fix missing virtual destructor new 83ec9b51ed2 [AIX] Use csect reference for function address constants The 13 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: .../clang-tidy/readability/MagicNumbersCheck.cpp | 8 +- .../clang-tidy/utils/FixItHintUtils.cpp | 1 + clang/include/clang/ASTMatchers/ASTMatchers.h | 11 + clang/include/clang/Basic/DiagnosticGroups.td | 2 +- clang/include/clang/Basic/arm_mve.td | 75 ++- clang/include/clang/Basic/arm_mve_defs.td | 5 +- clang/lib/AST/Expr.cpp | 2 +- clang/lib/ASTMatchers/ASTMatchersInternal.cpp | 5 + clang/lib/Driver/ToolChains/Gnu.cpp | 104 +++- clang/lib/Driver/ToolChains/Gnu.h | 9 + clang/lib/Driver/ToolChains/Hurd.cpp | 6 +- clang/lib/Driver/ToolChains/Hurd.h | 4 + clang/lib/Driver/ToolChains/Linux.cpp | 77 +-- clang/lib/Driver/ToolChains/Linux.h | 7 +- clang/lib/Format/UnwrappedLineFormatter.cpp | 13 + clang/lib/Lex/LiteralSupport.cpp | 8 +- .../CodeGen/arm-mve-intrinsics/scatter-gather.c | 60 +- clang/test/CodeGen/arm-mve-intrinsics/vabdq.c | 18 +- clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c | 18 +- clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c | 12 +- clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c | 8 +- clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c | 18 +- clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c | 8 +- clang/test/CodeGen/arm-mve-intrinsics/vminq.c | 14 +- clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c | 18 +- clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c | 24 +- clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c | 18 +- clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c | 6 +- clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c | 6 +- clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c | 20 +- clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c | 18 +- clang/test/Driver/cross-linux.c | 3 + clang/test/Misc/warning-wall.c | 4 +- clang/test/Sema/arm-mve-immediates.c | 28 +- clang/test/SemaCXX/warn-range-loop-analysis.cpp | 1 + .../ASTMatchers/ASTMatchersTraversalTest.cpp | 32 + clang/unittests/Format/FormatTest.cpp | 37 +- clang/utils/TableGen/MveEmitter.cpp | 11 +- libc/utils/HdrGen/CMakeLists.txt | 1 + libc/utils/HdrGen/Command.cpp | 15 + libc/utils/HdrGen/Command.h | 2 + .../NetBSD/NativeRegisterContextNetBSD_x86_64.cpp | 5 - llvm/bindings/ocaml/llvm/llvm.mli | 2 +- llvm/include/llvm/ADT/APFloat.h | 11 +- llvm/include/llvm/ADT/PointerUnion.h | 2 +- llvm/include/llvm/Analysis/ValueTracking.h | 4 +- .../include/llvm/CodeGen/GlobalISel/CallLowering.h | 2 +- llvm/include/llvm/DebugInfo/GSYM/FunctionInfo.h | 2 +- llvm/include/llvm/DebugInfo/GSYM/GsymCreator.h | 6 +- .../llvm/ExecutionEngine/Orc/OrcABISupport.h | 2 +- llvm/include/llvm/IR/InstrTypes.h | 2 +- llvm/include/llvm/IR/IntrinsicsARM.td | 61 +- llvm/include/llvm/IR/Metadata.h | 28 +- llvm/include/llvm/MC/MCCodeEmitter.h | 6 + llvm/include/llvm/MC/MCFragment.h | 92 +-- llvm/include/llvm/MC/MCSection.h | 13 - llvm/include/llvm/MC/MCSymbol.h | 10 +- llvm/include/llvm/Support/Allocator.h | 2 +- .../llvm/Target/GlobalISel/SelectionDAGCompat.td | 1 + llvm/include/llvm/Target/Target.td | 2 +- llvm/include/llvm/Transforms/IPO/Attributor.h | 6 +- llvm/lib/Analysis/AliasAnalysis.cpp | 5 + llvm/lib/Analysis/TypeBasedAliasAnalysis.cpp | 17 +- llvm/lib/Bitcode/Reader/MetadataLoader.cpp | 2 +- llvm/lib/CodeGen/Analysis.cpp | 2 +- llvm/lib/CodeGen/LiveDebugVariables.cpp | 2 +- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 17 +- .../CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp | 2 +- .../CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 2 +- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 2 +- llvm/lib/CodeGen/TwoAddressInstructionPass.cpp | 2 +- llvm/lib/DebugInfo/DWARF/DWARFDebugLine.cpp | 2 +- llvm/lib/IR/Metadata.cpp | 1 + llvm/lib/MC/MCAssembler.cpp | 14 +- llvm/lib/MC/MCExpr.cpp | 2 +- llvm/lib/MC/MCFragment.cpp | 6 +- llvm/lib/MC/MCObjectStreamer.cpp | 6 - llvm/lib/MC/MCParser/AsmParser.cpp | 3 +- llvm/lib/MC/MCParser/COFFAsmParser.cpp | 2 +- llvm/lib/MC/MCSection.cpp | 3 +- llvm/lib/ProfileData/GCOV.cpp | 2 +- llvm/lib/Support/APFloat.cpp | 155 +++-- llvm/lib/Support/StringRef.cpp | 10 +- llvm/lib/Target/AArch64/AArch64CallLowering.cpp | 2 +- llvm/lib/Target/AArch64/AArch64RegisterInfo.td | 2 +- .../Target/AArch64/AsmParser/AArch64AsmParser.cpp | 14 +- llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp | 2 +- .../Target/AMDGPU/AMDGPUInstructionSelector.cpp | 26 +- llvm/lib/Target/AMDGPU/AMDGPUInstructions.td | 22 +- .../Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 4 +- .../AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp | 1 + llvm/lib/Target/AMDGPU/R600AsmPrinter.cpp | 2 +- llvm/lib/Target/AMDGPU/SIInstructions.td | 41 +- llvm/lib/Target/ARM/ARMCallingConv.cpp | 2 +- llvm/lib/Target/ARM/ARMFastISel.cpp | 8 +- llvm/lib/Target/ARM/ARMFrameLowering.cpp | 6 +- llvm/lib/Target/ARM/ARMISelLowering.cpp | 2 +- llvm/lib/Target/ARM/ARMInstrMVE.td | 81 ++- llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp | 4 + llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 2 +- .../Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp | 7 +- .../lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.cpp | 2 +- llvm/lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.h | 2 +- llvm/lib/Target/ARM/MVETailPredication.cpp | 157 +++-- llvm/lib/Target/Hexagon/HexagonRegisterInfo.td | 2 +- llvm/lib/Target/Mips/MipsInstrFPU.td | 2 +- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp | 22 + llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp | 2 +- .../Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp | 222 ++++--- llvm/lib/Target/X86/X86ISelLowering.cpp | 291 ++++++--- llvm/lib/Target/X86/X86InstrAVX512.td | 2 +- llvm/lib/Target/X86/X86MCInstLower.cpp | 2 + llvm/lib/Target/X86/X86TargetTransformInfo.cpp | 4 + llvm/lib/Transforms/Coroutines/CoroSplit.cpp | 14 +- llvm/lib/Transforms/IPO/Attributor.cpp | 6 +- llvm/lib/Transforms/IPO/PartialInlining.cpp | 2 +- llvm/lib/Transforms/Utils/AddDiscriminators.cpp | 2 +- llvm/test/Analysis/CostModel/X86/uitofp.ll | 22 +- .../GlobalISel/inst-select-build-vector.v2s16.mir | 239 +++++++ .../AMDGPU/GlobalISel/inst-select-extract.mir | 20 + .../CodeGen/ARM/load_store_opt_clobber_cpsr.mir | 2 +- .../PowerPC/aix-reference-func-addr-const.ll | 32 + llvm/test/CodeGen/PowerPC/sext-vector-inreg.ll | 5 +- .../Thumb2/mve-intrinsics/scatter-gather.ll | 48 +- llvm/test/CodeGen/Thumb2/mve-intrinsics/vabdq.ll | 42 +- llvm/test/CodeGen/Thumb2/mve-intrinsics/vhaddq.ll | 40 +- llvm/test/CodeGen/Thumb2/mve-intrinsics/vhsubq.ll | 30 +- llvm/test/CodeGen/Thumb2/mve-intrinsics/vmaxnmq.ll | 16 +- llvm/test/CodeGen/Thumb2/mve-intrinsics/vmaxq.ll | 26 +- llvm/test/CodeGen/Thumb2/mve-intrinsics/vminnmq.ll | 16 +- llvm/test/CodeGen/Thumb2/mve-intrinsics/vminq.ll | 22 +- llvm/test/CodeGen/Thumb2/mve-intrinsics/vmulhq.ll | 40 +- llvm/test/CodeGen/Thumb2/mve-intrinsics/vmullbq.ll | 40 +- llvm/test/CodeGen/Thumb2/mve-intrinsics/vmulltq.ll | 40 +- llvm/test/CodeGen/Thumb2/mve-intrinsics/vqaddq.ll | 14 +- llvm/test/CodeGen/Thumb2/mve-intrinsics/vqsubq.ll | 14 +- llvm/test/CodeGen/Thumb2/mve-intrinsics/vrhaddq.ll | 42 +- llvm/test/CodeGen/Thumb2/mve-intrinsics/vrmulhq.ll | 40 +- llvm/test/CodeGen/Thumb2/segmented-stacks.ll | 86 ++- .../CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll | 2 +- .../CodeGen/X86/DynamicCalleeSavedRegisters.ll | 2 +- llvm/test/CodeGen/X86/combine-sdiv.ll | 203 +++--- llvm/test/CodeGen/X86/extractelement-load.ll | 45 ++ llvm/test/CodeGen/X86/lea.ll | 2 +- llvm/test/CodeGen/X86/masked_gather_scatter.ll | 2 +- llvm/test/CodeGen/X86/swifterror.ll | 2 +- llvm/test/CodeGen/X86/vec-strict-inttofp-128.ll | 41 +- llvm/test/CodeGen/X86/vec-strict-inttofp-256.ll | 150 ++--- llvm/test/CodeGen/X86/vec_int_to_fp.ll | 690 +++++++++------------ llvm/test/CodeGen/X86/vector-blend.ll | 38 +- .../X86/vector-constrained-fp-intrinsics.ll | 122 ++-- llvm/test/LTO/X86/parallel.ll | 2 +- llvm/test/MC/AArch64/arm64-directive_loh.s | 4 +- llvm/test/MC/ARM/misaligned-blx.s | 2 +- .../Transforms/Coroutines/coro-split-musttail.ll | 27 +- .../Transforms/Coroutines/coro-split-musttail1.ll | 104 ++++ .../test/Transforms/DeadArgElim/naked_functions.ll | 2 +- llvm/test/Transforms/SCCP/apint-basictest3.ll | 2 +- llvm/test/Transforms/SLPVectorizer/X86/align.ll | 2 +- llvm/test/Transforms/SROA/tbaa-struct.ll | 2 +- llvm/tools/llvm-c-test/echo.cpp | 4 +- llvm/tools/llvm-objdump/MachODump.cpp | 2 +- llvm/unittests/ADT/APFloatTest.cpp | 278 ++++----- llvm/unittests/Analysis/VectorFunctionABITest.cpp | 2 +- llvm/unittests/Analysis/VectorUtilsTest.cpp | 2 +- .../DebugInfo/DWARF/DWARFDebugLineTest.cpp | 38 +- .../WebAssembly/WebAssemblyExceptionInfoTest.cpp | 2 +- llvm/utils/TableGen/CodeGenTarget.cpp | 4 +- llvm/utils/TableGen/CodeGenTarget.h | 4 +- llvm/utils/bugpoint/RemoteRunSafely.sh | 2 +- mlir/CMakeLists.txt | 1 + mlir/docs/Dialects/SPIR-V.md | 119 +++- mlir/lib/Dialect/Linalg/Utils/Utils.cpp | 2 +- mlir/lib/IR/StandardTypes.cpp | 246 ++++---- mlir/test/AffineOps/memref-stride-calculation.mlir | 10 + polly/lib/Analysis/ScopGraphPrinter.cpp | 2 +- 176 files changed, 3018 insertions(+), 2239 deletions(-) create mode 100644 libc/utils/HdrGen/Command.cpp create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector.v2s16.mir create mode 100644 llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll create mode 100644 llvm/test/Transforms/Coroutines/coro-split-musttail1.ll -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 8 months

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