Tcwg-commits November 2024

tcwg-commits@lists.linaro.org

3 participants
1843 discussions

[gcc] branch releases/gcc-14 updated (9431ca6fcdb -> b1e14fc244c)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch releases/gcc-14 in repository gcc. from 9431ca6fcdb Daily bump. new 6cfe4fd3fb4 tree-optimization/117254 - ICE with access diangostics new bbe47a2d763 tree-optimization/117307 - STMT_VINFO_SLP_VECT_ONLY mis-com [...] new 8a13eef8874 tree-optimization/117333 - ICE with NULL access size DR new 1fce6796168 tree-optimization/117417 - ICE with complex load optimization new a8e01b735a1 middle-end/117433 - ICE with gimple BLKmode reg copy new 8764b8543b9 tree-optimization/117574 - bougs niter lt-to-ne new b1e14fc244c tree-optimization/117594 - fix live op vectorization for le [...] The 7 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/cfgexpand.cc | 7 ++++++- gcc/gimple-ssa-warn-access.cc | 3 ++- gcc/testsuite/gcc.dg/pr117254.c | 10 ++++++++++ gcc/testsuite/gcc.dg/pr117433.c | 21 +++++++++++++++++++++ gcc/testsuite/gcc.dg/torture/pr117333.c | 29 +++++++++++++++++++++++++++++ gcc/testsuite/gcc.dg/torture/pr117417.c | 16 ++++++++++++++++ gcc/testsuite/gcc.dg/torture/pr117574-1.c | 20 ++++++++++++++++++++ gcc/testsuite/gcc.dg/vect/pr117307.c | 17 +++++++++++++++++ gcc/testsuite/gcc.dg/vect/pr117594.c | 20 ++++++++++++++++++++ gcc/tree-data-ref.cc | 2 ++ gcc/tree-ssa-forwprop.cc | 4 ++-- gcc/tree-ssa-loop-niter.cc | 31 +++++++------------------------ gcc/tree-vect-data-refs.cc | 19 +++++++++++++------ gcc/tree-vect-loop.cc | 3 ++- 14 files changed, 167 insertions(+), 35 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/pr117254.c create mode 100644 gcc/testsuite/gcc.dg/pr117433.c create mode 100644 gcc/testsuite/gcc.dg/torture/pr117333.c create mode 100644 gcc/testsuite/gcc.dg/torture/pr117417.c create mode 100644 gcc/testsuite/gcc.dg/torture/pr117574-1.c create mode 100644 gcc/testsuite/gcc.dg/vect/pr117307.c create mode 100644 gcc/testsuite/gcc.dg/vect/pr117594.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 weeks, 2 days

[glibc] branch master updated (2d6427a63c -> e2436d6f5a)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository glibc. from 2d6427a63c benchtests: Add calloc test new a08d9a52f9 AArch64: Remove zva_128 from memset new e2436d6f5a malloc: send freed small chunks to smallbin The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: malloc/malloc.c | 53 +++++++++++++++++++++++++++++++----------------- sysdeps/aarch64/memset.S | 25 +---------------------- 2 files changed, 35 insertions(+), 43 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 weeks, 2 days

[gcc] branch master updated (b6a51390979 -> fe29b03825c)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from b6a51390979 c: Correct type compatibility for bit-fields [PR117828] new 356bfe8ca12 RISC-V: Add intrinsics support for SiFive Xsfvqmaccqoq/dod [...] new fe29b03825c RISC-V: Add intrinsics testcases for SiFive Xsfvqmaccqoq/do [...] The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/config.gcc | 2 +- gcc/config/riscv/generic-vector-ooo.md | 2 +- gcc/config/riscv/genrvv-type-indexer.cc | 47 +++++ gcc/config/riscv/riscv-vector-builtins-shapes.cc | 30 +++ gcc/config/riscv/riscv-vector-builtins-shapes.h | 2 + gcc/config/riscv/riscv-vector-builtins-types.def | 12 ++ gcc/config/riscv/riscv-vector-builtins.cc | 151 ++++++++++++++- gcc/config/riscv/riscv-vector-builtins.def | 26 ++- gcc/config/riscv/riscv-vector-builtins.h | 14 ++ gcc/config/riscv/riscv.md | 4 +- gcc/config/riscv/sifive-vector-builtins-bases.cc | 164 ++++++++++++++++ .../sifive-vector-builtins-bases.h} | 25 ++- .../riscv/sifive-vector-builtins-functions.def | 54 ++++++ gcc/config/riscv/sifive-vector.md | 164 ++++++++++++++++ gcc/config/riscv/t-riscv | 20 ++ gcc/config/riscv/vector-iterators.md | 32 ++++ gcc/config/riscv/vector.md | 1 + gcc/testsuite/gcc.target/riscv/rvv/rvv.exp | 2 + .../riscv/rvv/xsfvector/sf_vqmacc_2x8x2.c | 213 +++++++++++++++++++++ .../riscv/rvv/xsfvector/sf_vqmacc_4x8x4.c | 213 +++++++++++++++++++++ .../riscv/rvv/xsfvector/sf_vqmaccsu_2x8x2.c | 213 +++++++++++++++++++++ .../riscv/rvv/xsfvector/sf_vqmaccsu_4x8x4.c | 213 +++++++++++++++++++++ .../riscv/rvv/xsfvector/sf_vqmaccu_2x8x2.c | 213 +++++++++++++++++++++ .../riscv/rvv/xsfvector/sf_vqmaccu_4x8x4.c | 213 +++++++++++++++++++++ .../riscv/rvv/xsfvector/sf_vqmaccus_2x8x2.c | 213 +++++++++++++++++++++ .../riscv/rvv/xsfvector/sf_vqmaccus_4x8x4.c | 213 +++++++++++++++++++++ 26 files changed, 2428 insertions(+), 28 deletions(-) create mode 100644 gcc/config/riscv/sifive-vector-builtins-bases.cc copy gcc/config/{aarch64/aarch64-neon-sve-bridge-builtins.def => riscv/sifive-vect [...] create mode 100644 gcc/config/riscv/sifive-vector-builtins-functions.def create mode 100644 gcc/config/riscv/sifive-vector.md create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmacc_2x8x2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmacc_4x8x4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmaccsu_2x8x2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmaccsu_4x8x4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmaccu_2x8x2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmaccu_4x8x4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmaccus_2x8x2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmaccus_4x8x4.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 weeks, 2 days

[gcc] branch master updated (5b0e4ed3081 -> b6a51390979)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 5b0e4ed3081 AArch64: Suppress default options when march or mcpu used i [...] new b6a51390979 c: Correct type compatibility for bit-fields [PR117828] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/c/c-typeck.cc | 17 +++++++++- gcc/testsuite/gcc.dg/c23-tag-bitfields-1.c | 51 ++++++++++++++++++++++++++++++ gcc/testsuite/gcc.dg/pr117828.c | 14 ++++++++ 3 files changed, 81 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.dg/c23-tag-bitfields-1.c create mode 100644 gcc/testsuite/gcc.dg/pr117828.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 weeks, 2 days

[gcc] branch master updated (7028b1b368a -> 5b0e4ed3081)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 7028b1b368a aarch64: Add ISA requirements to some SVE/SME md comments new 5b0e4ed3081 AArch64: Suppress default options when march or mcpu used i [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/common/config/aarch64/aarch64-common.cc | 27 +++++++++++ gcc/config/aarch64/aarch64-elf-raw.h | 8 ++++ gcc/config/aarch64/aarch64-errata.h | 53 ++++++++++++++++++---- gcc/config/aarch64/aarch64-freebsd.h | 8 ++++ gcc/config/aarch64/aarch64-gnu.h | 7 +++ gcc/config/aarch64/aarch64-linux.h | 8 +++- gcc/config/aarch64/aarch64-netbsd.h | 9 ++++ gcc/config/aarch64/aarch64.h | 7 ++- gcc/config/aarch64/driver-aarch64.cc | 1 - gcc/doc/invoke.texi | 9 +++- .../aarch64/cpunative/{info_0 => info_30} | 2 +- .../aarch64/cpunative/{info_20 => info_31} | 2 +- .../aarch64/cpunative/{info_0 => info_32} | 2 +- .../aarch64/cpunative/{info_20 => info_33} | 2 +- .../gcc.target/aarch64/cpunative/native_cpu_30.c | 14 ++++++ .../gcc.target/aarch64/cpunative/native_cpu_31.c | 14 ++++++ .../gcc.target/aarch64/cpunative/native_cpu_32.c | 14 ++++++ .../gcc.target/aarch64/cpunative/native_cpu_33.c | 14 ++++++ gcc/testsuite/gcc.target/aarch64/erratas_opt_0.c | 10 ++++ gcc/testsuite/gcc.target/aarch64/erratas_opt_1.c | 11 +++++ gcc/testsuite/gcc.target/aarch64/erratas_opt_10.c | 10 ++++ gcc/testsuite/gcc.target/aarch64/erratas_opt_11.c | 10 ++++ gcc/testsuite/gcc.target/aarch64/erratas_opt_12.c | 10 ++++ gcc/testsuite/gcc.target/aarch64/erratas_opt_13.c | 11 +++++ gcc/testsuite/gcc.target/aarch64/erratas_opt_14.c | 11 +++++ gcc/testsuite/gcc.target/aarch64/erratas_opt_15.c | 11 +++++ gcc/testsuite/gcc.target/aarch64/erratas_opt_2.c | 10 ++++ gcc/testsuite/gcc.target/aarch64/erratas_opt_3.c | 10 ++++ gcc/testsuite/gcc.target/aarch64/erratas_opt_4.c | 10 ++++ gcc/testsuite/gcc.target/aarch64/erratas_opt_5.c | 11 +++++ gcc/testsuite/gcc.target/aarch64/erratas_opt_6.c | 11 +++++ gcc/testsuite/gcc.target/aarch64/erratas_opt_7.c | 11 +++++ gcc/testsuite/gcc.target/aarch64/erratas_opt_8.c | 10 ++++ gcc/testsuite/gcc.target/aarch64/erratas_opt_9.c | 11 +++++ 34 files changed, 350 insertions(+), 19 deletions(-) copy gcc/testsuite/gcc.target/aarch64/cpunative/{info_0 => info_30} (91%) copy gcc/testsuite/gcc.target/aarch64/cpunative/{info_20 => info_31} (96%) copy gcc/testsuite/gcc.target/aarch64/cpunative/{info_0 => info_32} (91%) copy gcc/testsuite/gcc.target/aarch64/cpunative/{info_20 => info_33} (96%) create mode 100644 gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_30.c create mode 100644 gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_31.c create mode 100644 gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_32.c create mode 100644 gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_33.c create mode 100644 gcc/testsuite/gcc.target/aarch64/erratas_opt_0.c create mode 100644 gcc/testsuite/gcc.target/aarch64/erratas_opt_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/erratas_opt_10.c create mode 100644 gcc/testsuite/gcc.target/aarch64/erratas_opt_11.c create mode 100644 gcc/testsuite/gcc.target/aarch64/erratas_opt_12.c create mode 100644 gcc/testsuite/gcc.target/aarch64/erratas_opt_13.c create mode 100644 gcc/testsuite/gcc.target/aarch64/erratas_opt_14.c create mode 100644 gcc/testsuite/gcc.target/aarch64/erratas_opt_15.c create mode 100644 gcc/testsuite/gcc.target/aarch64/erratas_opt_2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/erratas_opt_3.c create mode 100644 gcc/testsuite/gcc.target/aarch64/erratas_opt_4.c create mode 100644 gcc/testsuite/gcc.target/aarch64/erratas_opt_5.c create mode 100644 gcc/testsuite/gcc.target/aarch64/erratas_opt_6.c create mode 100644 gcc/testsuite/gcc.target/aarch64/erratas_opt_7.c create mode 100644 gcc/testsuite/gcc.target/aarch64/erratas_opt_8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/erratas_opt_9.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 weeks, 2 days

[gcc] branch master updated (a54aa75ab30 -> 7028b1b368a)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from a54aa75ab30 tree-optimization/115438 - SLP reduction vect vs. bwaves new dfa78681851 aarch64: Add basic svmfloat8_t support to arm_sve.h new 49365994da6 aarch64: specify fpm mode in function instances and groups new 75c3a5c8e6c aarch64: add svcvt* FP8 intrinsics new 538204079b2 aarch64: add SVE2 FP8 multiply accumulate intrinsics new 441f8d637d7 aarch64: add SVE2 FP8DOT2 and FP8DOT4 intrinsics new 7028b1b368a aarch64: Add ISA requirements to some SVE/SME md comments The 6 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/config/aarch64/aarch64-option-extensions.def | 12 + gcc/config/aarch64/aarch64-sme.md | 72 ++--- gcc/config/aarch64/aarch64-sve-builtins-base.cc | 77 +++--- .../aarch64/aarch64-sve-builtins-functions.h | 16 +- gcc/config/aarch64/aarch64-sve-builtins-shapes.cc | 208 ++++++++++++++- gcc/config/aarch64/aarch64-sve-builtins-shapes.h | 12 +- gcc/config/aarch64/aarch64-sve-builtins-sve2.cc | 103 +++++-- gcc/config/aarch64/aarch64-sve-builtins-sve2.def | 43 +++ gcc/config/aarch64/aarch64-sve-builtins-sve2.h | 14 + gcc/config/aarch64/aarch64-sve-builtins.cc | 71 ++++- gcc/config/aarch64/aarch64-sve-builtins.def | 11 +- gcc/config/aarch64/aarch64-sve-builtins.h | 28 +- gcc/config/aarch64/aarch64-sve2.md | 283 ++++++++++++++++---- gcc/config/aarch64/aarch64.h | 32 +++ gcc/config/aarch64/iterators.md | 63 +++++ gcc/doc/invoke.texi | 17 ++ .../aarch64/sve/acle/general-c++/mangle_1.C | 2 + .../aarch64/sve/acle/general-c++/mangle_2.C | 2 + .../gcc.target/aarch64/sve/acle/asm/clasta_mf8.c | 52 ++++ .../gcc.target/aarch64/sve/acle/asm/clastb_mf8.c | 52 ++++ .../gcc.target/aarch64/sve/acle/asm/create2_1.c | 15 ++ .../gcc.target/aarch64/sve/acle/asm/create3_1.c | 11 + .../gcc.target/aarch64/sve/acle/asm/create4_1.c | 12 + .../gcc.target/aarch64/sve/acle/asm/dup_lane_mf8.c | 124 +++++++++ .../gcc.target/aarch64/sve/acle/asm/dup_mf8.c | 31 +++ .../aarch64/sve/acle/asm/dup_neonq_mf8.c | 30 +++ .../aarch64/sve/acle/asm/dupq_lane_mf8.c | 48 ++++ .../aarch64/sve/acle/asm/{ext_u8.c => ext_mf8.c} | 42 +-- .../gcc.target/aarch64/sve/acle/asm/get2_mf8.c | 55 ++++ .../gcc.target/aarch64/sve/acle/asm/get3_mf8.c | 108 ++++++++ .../gcc.target/aarch64/sve/acle/asm/get4_mf8.c | 179 +++++++++++++ .../aarch64/sve/acle/asm/get_neonq_mf8.c | 33 +++ .../gcc.target/aarch64/sve/acle/asm/insr_mf8.c | 22 ++ .../sve/acle/asm/{lasta_s16.c => lasta_mf8.c} | 8 +- .../sve/acle/asm/{lastb_s16.c => lastb_mf8.c} | 8 +- .../aarch64/sve/acle/asm/{ld1_s8.c => ld1_mf8.c} | 96 +++---- .../sve/acle/asm/{ld1ro_s8.c => ld1ro_mf8.c} | 72 ++--- .../gcc.target/aarch64/sve/acle/asm/ld1rq_mf8.c | 137 ++++++++++ .../aarch64/sve/acle/asm/{ld2_s8.c => ld2_mf8.c} | 120 ++++----- .../aarch64/sve/acle/asm/{ld3_s8.c => ld3_mf8.c} | 144 +++++----- .../aarch64/sve/acle/asm/{ld4_s8.c => ld4_mf8.c} | 168 ++++++------ .../sve/acle/asm/{ldff1_s8.c => ldff1_mf8.c} | 48 ++-- .../gcc.target/aarch64/sve/acle/asm/ldnf1_mf8.c | 155 +++++++++++ .../sve/acle/asm/{ldnt1_s8.c => ldnt1_mf8.c} | 96 +++---- .../aarch64/sve/acle/asm/{len_s8.c => len_mf8.c} | 6 +- .../aarch64/sve/acle/asm/reinterpret_bf16.c | 17 ++ .../aarch64/sve/acle/asm/reinterpret_f16.c | 17 ++ .../aarch64/sve/acle/asm/reinterpret_f32.c | 17 ++ .../aarch64/sve/acle/asm/reinterpret_f64.c | 17 ++ .../aarch64/sve/acle/asm/reinterpret_mf8.c | 297 +++++++++++++++++++++ .../aarch64/sve/acle/asm/reinterpret_s16.c | 17 ++ .../aarch64/sve/acle/asm/reinterpret_s32.c | 17 ++ .../aarch64/sve/acle/asm/reinterpret_s64.c | 17 ++ .../aarch64/sve/acle/asm/reinterpret_s8.c | 17 ++ .../aarch64/sve/acle/asm/reinterpret_u16.c | 28 ++ .../aarch64/sve/acle/asm/reinterpret_u32.c | 28 ++ .../aarch64/sve/acle/asm/reinterpret_u64.c | 28 ++ .../aarch64/sve/acle/asm/reinterpret_u8.c | 28 ++ .../aarch64/sve/acle/asm/{rev_s8.c => rev_mf8.c} | 12 +- .../aarch64/sve/acle/asm/{sel_s8.c => sel_mf8.c} | 18 +- .../gcc.target/aarch64/sve/acle/asm/set2_mf8.c | 41 +++ .../gcc.target/aarch64/sve/acle/asm/set3_mf8.c | 63 +++++ .../sve/acle/asm/{set4_s16.c => set4_mf8.c} | 48 ++-- .../aarch64/sve/acle/asm/set_neonq_mf8.c | 23 ++ .../sve/acle/asm/{splice_s8.c => splice_mf8.c} | 18 +- .../aarch64/sve/acle/asm/{st1_s8.c => st1_mf8.c} | 96 +++---- .../aarch64/sve/acle/asm/{st2_u8.c => st2_mf8.c} | 120 ++++----- .../aarch64/sve/acle/asm/{st3_s8.c => st3_mf8.c} | 144 +++++----- .../aarch64/sve/acle/asm/{st4_s8.c => st4_mf8.c} | 168 ++++++------ .../sve/acle/asm/{stnt1_s8.c => stnt1_mf8.c} | 96 +++---- .../gcc.target/aarch64/sve/acle/asm/tbl_mf8.c | 30 +++ .../aarch64/sve/acle/asm/test_sve_acle.h | 8 +- .../aarch64/sve/acle/asm/{trn1_s8.c => trn1_mf8.c} | 18 +- .../sve/acle/asm/{trn1q_f64.c => trn1q_mf8.c} | 20 +- .../aarch64/sve/acle/asm/{trn2_s8.c => trn2_mf8.c} | 18 +- .../sve/acle/asm/{trn2q_s16.c => trn2q_mf8.c} | 20 +- .../gcc.target/aarch64/sve/acle/asm/undef2_1.c | 7 + .../gcc.target/aarch64/sve/acle/asm/undef3_1.c | 7 + .../gcc.target/aarch64/sve/acle/asm/undef4_1.c | 7 + .../gcc.target/aarch64/sve/acle/asm/undef_1.c | 7 + .../aarch64/sve/acle/asm/{uzp1_s8.c => uzp1_mf8.c} | 18 +- .../sve/acle/asm/{uzp1q_s16.c => uzp1q_mf8.c} | 18 +- .../aarch64/sve/acle/asm/{uzp2_s8.c => uzp2_mf8.c} | 18 +- .../sve/acle/asm/{uzp2q_s16.c => uzp2q_mf8.c} | 20 +- .../aarch64/sve/acle/asm/{zip1_s8.c => zip1_mf8.c} | 18 +- .../sve/acle/asm/{zip1q_s16.c => zip1q_mf8.c} | 20 +- .../aarch64/sve/acle/asm/{zip2_s8.c => zip2_mf8.c} | 18 +- .../sve/acle/asm/{zip2q_s16.c => zip2q_mf8.c} | 20 +- .../aarch64/sve/acle/general-c/ternary_mfloat8_1.c | 33 +++ .../sve/acle/general-c/ternary_mfloat8_lane_1.c | 84 ++++++ .../ternary_mfloat8_lane_group_selection_1.c | 49 ++++ .../sve/acle/general-c/ternary_mfloat8_opt_n_1.c | 60 +++++ .../sve/acle/general-c/unary_convertxn_narrow_1.c | 60 +++++ .../sve/acle/general-c/unary_convertxn_narrowt_1.c | 38 +++ .../gcc.target/aarch64/sve/pcs/annotate_1.c | 8 + .../gcc.target/aarch64/sve/pcs/annotate_2.c | 8 + .../gcc.target/aarch64/sve/pcs/annotate_3.c | 8 + .../gcc.target/aarch64/sve/pcs/annotate_4.c | 12 + .../gcc.target/aarch64/sve/pcs/annotate_5.c | 12 + .../gcc.target/aarch64/sve/pcs/annotate_6.c | 12 + .../gcc.target/aarch64/sve/pcs/annotate_7.c | 8 + .../sve/pcs/{args_5_be_u8.c => args_5_be_mf8.c} | 14 +- .../sve/pcs/{args_5_le_s8.c => args_5_le_mf8.c} | 14 +- .../sve/pcs/{args_6_be_s8.c => args_6_be_mf8.c} | 30 +-- .../sve/pcs/{args_6_le_s8.c => args_6_le_mf8.c} | 30 +-- .../gcc.target/aarch64/sve/pcs/gnu_vectors_1.c | 12 +- .../gcc.target/aarch64/sve/pcs/gnu_vectors_2.c | 10 +- .../gcc.target/aarch64/sve/pcs/return_4.c | 21 +- .../gcc.target/aarch64/sve/pcs/return_4_1024.c | 21 +- .../gcc.target/aarch64/sve/pcs/return_4_128.c | 21 +- .../gcc.target/aarch64/sve/pcs/return_4_2048.c | 21 +- .../gcc.target/aarch64/sve/pcs/return_4_256.c | 21 +- .../gcc.target/aarch64/sve/pcs/return_4_512.c | 21 +- .../gcc.target/aarch64/sve/pcs/return_5.c | 21 +- .../gcc.target/aarch64/sve/pcs/return_5_1024.c | 21 +- .../gcc.target/aarch64/sve/pcs/return_5_128.c | 21 +- .../gcc.target/aarch64/sve/pcs/return_5_2048.c | 21 +- .../gcc.target/aarch64/sve/pcs/return_5_256.c | 21 +- .../gcc.target/aarch64/sve/pcs/return_5_512.c | 21 +- .../gcc.target/aarch64/sve/pcs/return_6.c | 24 ++ .../gcc.target/aarch64/sve/pcs/return_6_1024.c | 22 ++ .../gcc.target/aarch64/sve/pcs/return_6_128.c | 19 ++ .../gcc.target/aarch64/sve/pcs/return_6_2048.c | 22 ++ .../gcc.target/aarch64/sve/pcs/return_6_256.c | 22 ++ .../gcc.target/aarch64/sve/pcs/return_6_512.c | 22 ++ .../gcc.target/aarch64/sve/pcs/return_7.c | 28 ++ .../gcc.target/aarch64/sve/pcs/return_8.c | 29 ++ .../gcc.target/aarch64/sve/pcs/return_9.c | 33 +++ .../sve/pcs/{varargs_2_s8.c => varargs_2_mf8.c} | 70 +++-- .../gcc.target/aarch64/sve2/acle/asm/cvt_mf8.c | 48 ++++ .../gcc.target/aarch64/sve2/acle/asm/cvtlt_mf8.c | 50 ++++ .../gcc.target/aarch64/sve2/acle/asm/cvtn_mf8.c | 30 +++ .../gcc.target/aarch64/sve2/acle/asm/cvtnb_mf8.c | 20 ++ .../gcc.target/aarch64/sve2/acle/asm/cvtnt_mf8.c | 31 +++ .../aarch64/sve2/acle/asm/dot_lane_mf8.c | 172 ++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/dot_mf8.c | 101 +++++++ .../aarch64/sve2/acle/asm/mlalb_lane_mf8.c | 91 +++++++ .../gcc.target/aarch64/sve2/acle/asm/mlalb_mf8.c | 78 ++++++ .../aarch64/sve2/acle/asm/mlallbb_lane_mf8.c | 91 +++++++ .../gcc.target/aarch64/sve2/acle/asm/mlallbb_mf8.c | 78 ++++++ .../aarch64/sve2/acle/asm/mlallbt_lane_mf8.c | 91 +++++++ .../gcc.target/aarch64/sve2/acle/asm/mlallbt_mf8.c | 78 ++++++ .../aarch64/sve2/acle/asm/mlalltb_lane_mf8.c | 91 +++++++ .../gcc.target/aarch64/sve2/acle/asm/mlalltb_mf8.c | 78 ++++++ .../aarch64/sve2/acle/asm/mlalltt_lane_mf8.c | 91 +++++++ .../gcc.target/aarch64/sve2/acle/asm/mlalltt_mf8.c | 78 ++++++ .../aarch64/sve2/acle/asm/mlalt_lane_mf8.c | 91 +++++++ .../gcc.target/aarch64/sve2/acle/asm/mlalt_mf8.c | 78 ++++++ .../gcc.target/aarch64/sve2/acle/asm/tbl2_mf8.c | 31 +++ .../aarch64/sve2/acle/asm/{tbx_u8.c => tbx_mf8.c} | 20 +- .../gcc.target/aarch64/sve2/acle/asm/whilerw_mf8.c | 50 ++++ .../gcc.target/aarch64/sve2/acle/asm/whilewr_mf8.c | 50 ++++ gcc/testsuite/lib/target-supports.exp | 4 +- 153 files changed, 6124 insertions(+), 1164 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clasta_mf8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clastb_mf8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_lane_mf8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_mf8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_neonq_mf8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_lane_mf8.c copy gcc/testsuite/gcc.target/aarch64/sve/acle/asm/{ext_u8.c => ext_mf8.c} (53%) create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get2_mf8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get3_mf8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get4_mf8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get_neonq_mf8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/insr_mf8.c copy gcc/testsuite/gcc.target/aarch64/sve/acle/asm/{lasta_s16.c => lasta_mf8.c} (51%) copy gcc/testsuite/gcc.target/aarch64/sve/acle/asm/{lastb_s16.c => lastb_mf8.c} (51%) copy gcc/testsuite/gcc.target/aarch64/sve/acle/asm/{ld1_s8.c => ld1_mf8.c} (53%) copy gcc/testsuite/gcc.target/aarch64/sve/acle/asm/{ld1ro_s8.c => ld1ro_mf8.c} (53%) create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_mf8.c copy gcc/testsuite/gcc.target/aarch64/sve/acle/asm/{ld2_s8.c => ld2_mf8.c} (56%) copy gcc/testsuite/gcc.target/aarch64/sve/acle/asm/{ld3_s8.c => ld3_mf8.c} (55%) copy gcc/testsuite/gcc.target/aarch64/sve/acle/asm/{ld4_s8.c => ld4_mf8.c} (55%) copy gcc/testsuite/gcc.target/aarch64/sve/acle/asm/{ldff1_s8.c => ldff1_mf8.c} (58%) create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1_mf8.c copy gcc/testsuite/gcc.target/aarch64/sve/acle/asm/{ldnt1_s8.c => ldnt1_mf8.c} (52%) copy gcc/testsuite/gcc.target/aarch64/sve/acle/asm/{len_s8.c => len_mf8.c} (60%) create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/reinterpret_mf8.c copy gcc/testsuite/gcc.target/aarch64/sve/acle/asm/{rev_s8.c => rev_mf8.c} (53%) copy gcc/testsuite/gcc.target/aarch64/sve/acle/asm/{sel_s8.c => sel_mf8.c} (52%) create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set2_mf8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set3_mf8.c copy gcc/testsuite/gcc.target/aarch64/sve/acle/asm/{set4_s16.c => set4_mf8.c} (50%) create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set_neonq_mf8.c copy gcc/testsuite/gcc.target/aarch64/sve/acle/asm/{splice_s8.c => splice_mf8.c} (56%) copy gcc/testsuite/gcc.target/aarch64/sve/acle/asm/{st1_s8.c => st1_mf8.c} (52%) copy gcc/testsuite/gcc.target/aarch64/sve/acle/asm/{st2_u8.c => st2_mf8.c} (56%) copy gcc/testsuite/gcc.target/aarch64/sve/acle/asm/{st3_s8.c => st3_mf8.c} (54%) copy gcc/testsuite/gcc.target/aarch64/sve/acle/asm/{st4_s8.c => st4_mf8.c} (55%) copy gcc/testsuite/gcc.target/aarch64/sve/acle/asm/{stnt1_s8.c => stnt1_mf8.c} (52%) create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tbl_mf8.c copy gcc/testsuite/gcc.target/aarch64/sve/acle/asm/{trn1_s8.c => trn1_mf8.c} (51%) copy gcc/testsuite/gcc.target/aarch64/sve/acle/asm/{trn1q_f64.c => trn1q_mf8.c} (62%) copy gcc/testsuite/gcc.target/aarch64/sve/acle/asm/{trn2_s8.c => trn2_mf8.c} (51%) copy gcc/testsuite/gcc.target/aarch64/sve/acle/asm/{trn2q_s16.c => trn2q_mf8.c} (62%) copy gcc/testsuite/gcc.target/aarch64/sve/acle/asm/{uzp1_s8.c => uzp1_mf8.c} (51%) copy gcc/testsuite/gcc.target/aarch64/sve/acle/asm/{uzp1q_s16.c => uzp1q_mf8.c} (62%) copy gcc/testsuite/gcc.target/aarch64/sve/acle/asm/{uzp2_s8.c => uzp2_mf8.c} (51%) copy gcc/testsuite/gcc.target/aarch64/sve/acle/asm/{uzp2q_s16.c => uzp2q_mf8.c} (62%) copy gcc/testsuite/gcc.target/aarch64/sve/acle/asm/{zip1_s8.c => zip1_mf8.c} (51%) copy gcc/testsuite/gcc.target/aarch64/sve/acle/asm/{zip1q_s16.c => zip1q_mf8.c} (62%) copy gcc/testsuite/gcc.target/aarch64/sve/acle/asm/{zip2_s8.c => zip2_mf8.c} (51%) copy gcc/testsuite/gcc.target/aarch64/sve/acle/asm/{zip2q_s16.c => zip2q_mf8.c} (62%) create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/ternary_mfl [...] create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/ternary_mfl [...] create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/ternary_mfl [...] create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/ternary_mfl [...] create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unary_conve [...] create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unary_conve [...] copy gcc/testsuite/gcc.target/aarch64/sve/pcs/{args_5_be_u8.c => args_5_be_mf8.c} (85%) copy gcc/testsuite/gcc.target/aarch64/sve/pcs/{args_5_le_s8.c => args_5_le_mf8.c} (84%) copy gcc/testsuite/gcc.target/aarch64/sve/pcs/{args_6_be_s8.c => args_6_be_mf8.c} (74%) copy gcc/testsuite/gcc.target/aarch64/sve/pcs/{args_6_le_s8.c => args_6_le_mf8.c} (74%) copy gcc/testsuite/gcc.target/aarch64/sve/pcs/{varargs_2_s8.c => varargs_2_mf8.c} (60%) create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/cvt_mf8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/cvtlt_mf8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/cvtn_mf8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/cvtnb_mf8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/cvtnt_mf8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/dot_lane_mf8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/dot_mf8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/mlalb_lane_mf8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/mlalb_mf8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/mlallbb_lane_mf8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/mlallbb_mf8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/mlallbt_lane_mf8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/mlallbt_mf8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/mlalltb_lane_mf8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/mlalltb_mf8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/mlalltt_lane_mf8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/mlalltt_mf8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/mlalt_lane_mf8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/mlalt_mf8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/tbl2_mf8.c copy gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/{tbx_u8.c => tbx_mf8.c} (55%) create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/whilerw_mf8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/whilewr_mf8.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 weeks, 2 days

[gcc] branch master updated (b5df3eefd70 -> a54aa75ab30)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from b5df3eefd70 cp: Fix another assumption in the FE about constant vector [...] new a54aa75ab30 tree-optimization/115438 - SLP reduction vect vs. bwaves The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/tree-vect-loop.cc | 14 ++++++++++++++ 1 file changed, 14 insertions(+) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 weeks, 2 days

[gcc] branch master updated (5a6af707f0a -> b5df3eefd70)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 5a6af707f0a aarch64: add ACLE macro _CHKFEAT_GCS new 65df27bb0ca aarch64: Fix ACLE macro __ARM_FEATURE_SVE_VECTOR_OPERATORS new 761cf602188 aarch64: Make C/C++ operations possible on SVE ACLE types. new 47fa008ad88 c: Range-check indexing of SVE ACLE vectors new 4f593db8803 gimple: Handle variable-sized vectors in BIT_FIELD_REF new 17b520a10cd c: Fix constructor bounds checking for VLA and construct VL [...] new 91fb1da11f4 aarch64: Add testcase for C/C++ ops on SVE ACLE types. new 6338716fe8d aarch64: Update SVE ACLE tests new b5df3eefd70 cp: Fix another assumption in the FE about constant vector [...] The 8 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/c-family/c-common.cc | 10 +- gcc/c/c-typeck.cc | 16 +- gcc/config/aarch64/aarch64-c.cc | 10 +- gcc/config/aarch64/aarch64-sve-builtins.cc | 5 +- gcc/cp/decl.cc | 11 +- gcc/gimple-fold.cc | 2 +- gcc/testsuite/g++.dg/ext/sve-sizeless-1.C | 11 + gcc/testsuite/g++.dg/ext/sve-sizeless-2.C | 9 + .../aarch64/sve/acle/general-c++/gnu_vectors_1.C | 438 ++++++++-------- .../aarch64/sve/acle/general-c++/gnu_vectors_2.C | 434 +++++++-------- .../aarch64/sve/acle/general-c/gnu_vectors_1.c | 349 ++++++------- .../aarch64/sve/acle/general-c/gnu_vectors_2.c | 346 ++++++------ .../aarch64/sve/acle/general-c/sizeless-1.c | 15 +- .../aarch64/sve/acle/general-c/sizeless-2.c | 14 +- .../aarch64/sve/acle/general/attributes_7.c | 30 +- .../gcc.target/aarch64/sve/acle/general/cops.c | 579 +++++++++++++++++++++ gcc/tree-cfg.cc | 2 +- gcc/tree.cc | 16 +- 18 files changed, 1474 insertions(+), 823 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/cops.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 weeks, 2 days

[glibc] branch master updated (19a198f058 -> 2d6427a63c)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository glibc. from 19a198f058 pthread_getcpuclockid: Add descriptive comment to smoke test new 2d6427a63c benchtests: Add calloc test The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: benchtests/Makefile | 7 ++++++- malloc/tst-malloc-random.c => benchtests/bench-calloc-simple.c | 8 +++++--- malloc/tst-malloc-random.c => benchtests/bench-calloc-thread.c | 8 +++++--- benchtests/bench-malloc-simple.c | 9 +++++++-- benchtests/bench-malloc-thread.c | 9 +++++++-- 5 files changed, 30 insertions(+), 11 deletions(-) copy malloc/tst-malloc-random.c => benchtests/bench-calloc-simple.c (84%) copy malloc/tst-malloc-random.c => benchtests/bench-calloc-thread.c (84%) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 weeks, 2 days

[toolchain/ci/interesting-commits] branch master updated (9dd04cb70 -> d0c8817fc)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch master in repository toolchain/ci/interesting-commits. from 9dd04cb70 Add entry 471c71be0fe507ecb02b5a9650e882f261ecc979 from https [...] new d0c8817fc Add entry 471c71be0fe507ecb02b5a9650e882f261ecc979 from https [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: .../jira/description | 4 + .../jira/yaml | 4 + .../status.txt | 4 + .../details.txt | 158 ++++++++++----------- .../reproduction_instructions.txt | 0 .../reproduction_instructions_with_ci_script.txt | 4 +- .../main-aarch64-O0-debug}/status-summary.txt | 2 +- .../main-aarch64-O0-debug/status.txt | 3 + .../tcwg_flang_test/status.txt | 4 + 9 files changed, 101 insertions(+), 82 deletions(-) copy fujitsu_testsuite/sha1/471c71be0fe507ecb02b5a9650e882f261ecc979/tcwg_flang_te [...] copy fujitsu_testsuite/sha1/{a0e269d5d279c3a0781bb74940cf5ec16b4ab109 => 471c71be0 [...] copy fujitsu_testsuite/sha1/471c71be0fe507ecb02b5a9650e882f261ecc979/tcwg_flang_te [...] copy {gcc/sha1/021077b94741c9300dfff3a24e95b3ffa3f508a7 => fujitsu_testsuite/sha1/ [...] create mode 100644 fujitsu_testsuite/sha1/471c71be0fe507ecb02b5a9650e882f261ecc979 [...] -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 weeks, 2 days

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