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from d1318ebb7d1 libstdc++: Make std::vector<bool> constructor noexcept (LWG 3778)
new d777d66cc16 aarch64: Fix fp8 cpuinfo feature names
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gcc/config/aarch64/aarch64-option-extensions.def | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
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from a3a47415b74 gas: partly restore how current_location() had worked
new 6da18427700 gdb: fix comment for gdbarch_stack_grows_down
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gdb/gdbarch.h | 2 +-
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from 29bea6921d0 libstdc++: Fix constraints on std::optional converting cons [...]
new d1318ebb7d1 libstdc++: Make std::vector<bool> constructor noexcept (LWG 3778)
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libstdc++-v3/include/bits/stl_bvector.h | 2 +-
.../23_containers/vector/bool/cons/lwg3778.cc | 87 ++++++++++++++++++++++
2 files changed, 88 insertions(+), 1 deletion(-)
create mode 100644 libstdc++-v3/testsuite/23_containers/vector/bool/cons/lwg3778.cc
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from 3d72e50caeb OpenMP: 'allocate' directive - fixes for 'alignof' and [[om [...]
new 0b89341f124 bitintlower: Fix up ?ROTATE_EXPR lowering [PR117847]
new 17c9c7c10a7 tree-ssanames, match.pd: get_nonzero_bits/with_*_nonzero_bi [...]
new 29bea6921d0 libstdc++: Fix constraints on std::optional converting cons [...]
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gcc/gimple-lower-bitint.cc | 13 +++-
gcc/match.pd | 45 +++++++-----
gcc/testsuite/gcc.dg/torture/bitint-75.c | 27 +++++++
gcc/testsuite/gcc.dg/tree-ssa/pr117420.c | 16 +++++
gcc/tree-ssanames.cc | 84 +++++++++++++++++++++-
gcc/tree-ssanames.h | 1 +
libstdc++-v3/include/std/optional | 4 +-
.../20_util/optional/assignment/117858.cc | 17 -----
.../testsuite/20_util/optional/cons/117858.cc | 23 ++++++
9 files changed, 190 insertions(+), 40 deletions(-)
create mode 100644 gcc/testsuite/gcc.dg/torture/bitint-75.c
create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr117420.c
delete mode 100644 libstdc++-v3/testsuite/20_util/optional/assignment/117858.cc
create mode 100644 libstdc++-v3/testsuite/20_util/optional/cons/117858.cc
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from 83f22c1c526 aarch64: Add flags field to aarch64-simd-pragma-builtins.def
new 3d72e50caeb OpenMP: 'allocate' directive - fixes for 'alignof' and [[om [...]
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gcc/c/c-parser.cc | 5 +--
gcc/cgraphunit.cc | 12 ++++++
gcc/fortran/trans-decl.cc | 3 --
gcc/testsuite/c-c++-common/gomp/allocate-18.c | 6 +--
gcc/testsuite/c-c++-common/gomp/allocate-19.c | 10 ++---
libgomp/libgomp.texi | 6 +++
libgomp/testsuite/libgomp.c/allocate-7.c | 54 +++++++++++++++++++++++++++
7 files changed, 81 insertions(+), 15 deletions(-)
create mode 100644 libgomp/testsuite/libgomp.c/allocate-7.c
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from f2d91164a5c Match: Refactor the unsigned SAT_SUB match patterns [NFC]
new e8fc954631a aarch64: Move some diagnostic functions to aarch64.cc
new 5f3282f726b aarch64: Split out aarch64_v64_mode
new c063f833c66 aarch64: Put iterators into the right section
new f855bc3006f aarch64: Refactor AdvSIMD intrinsics
new a07a2b8c9e7 aarch64: Add support for AdvSIMD lut
new 83f22c1c526 aarch64: Add flags field to aarch64-simd-pragma-builtins.def
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gcc/config/aarch64/aarch64-builtins.cc | 244 +++++-
gcc/config/aarch64/aarch64-option-extensions.def | 2 +
gcc/config/aarch64/aarch64-protos.h | 15 +-
.../aarch64/aarch64-simd-pragma-builtins.def | 69 +-
gcc/config/aarch64/aarch64-simd.md | 25 +
gcc/config/aarch64/aarch64-sve-builtins-base.cc | 8 +-
gcc/config/aarch64/aarch64-sve-builtins.cc | 65 +-
gcc/config/aarch64/aarch64.cc | 116 ++-
gcc/config/aarch64/aarch64.h | 3 +
gcc/config/aarch64/iterators.md | 117 +--
gcc/doc/invoke.texi | 2 +
.../gcc.target/aarch64/simd/lut-incorrect-range.c | 221 ++++++
.../gcc.target/aarch64/simd/lut-no-flag.c | 10 +
gcc/testsuite/gcc.target/aarch64/simd/lut.c | 849 +++++++++++++++++++++
14 files changed, 1569 insertions(+), 177 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/lut-incorrect-range.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/lut-no-flag.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/lut.c
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unknown user pushed a change to branch master
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from 98439a80cce Support Intel AVX10.2 BF16 instructions
new 29f84cf8a21 gas: streamline expr_build_dot()
new 5ea62b98d95 MMIX: use current_location() directly
new a3a47415b74 gas: partly restore how current_location() had worked
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gas/config/tc-i386-intel.c | 6 ++++--
gas/config/tc-i386.c | 9 ++++++---
gas/config/tc-i386.h | 4 ++--
gas/config/tc-mmix.c | 10 ----------
gas/config/tc-mmix.h | 9 +++------
gas/expr.c | 47 ++++++++++++++++++++++++++++++----------------
gas/expr.h | 2 +-
7 files changed, 47 insertions(+), 40 deletions(-)
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from 5cbeecf07df RISC-V: Fix incorrect optimization options passing to reduc [...]
new f2d91164a5c Match: Refactor the unsigned SAT_SUB match patterns [NFC]
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gcc/match.pd | 203 ++++++++++++++++++++++++++---------------------------------
1 file changed, 89 insertions(+), 114 deletions(-)
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from 4acab372d31 replace atoi with strtoul in varasm.cc (decode_reg_name_and [...]
new 5cbeecf07df RISC-V: Fix incorrect optimization options passing to reduc [...]
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gcc/testsuite/gcc.target/riscv/rvv/rvv.exp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
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from be8d1a358e3 tree-optimization/117874 - missed vectorization that's form [...]
new 4acab372d31 replace atoi with strtoul in varasm.cc (decode_reg_name_and [...]
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gcc/testsuite/gcc.dg/pr114540.c | 31 +++++++++++++++++++++++++++++++
gcc/varasm.cc | 23 ++++++++++++++---------
2 files changed, 45 insertions(+), 9 deletions(-)
create mode 100644 gcc/testsuite/gcc.dg/pr114540.c
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