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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_cross/gnu-master-aarch64-build_cross in repository toolchain/ci/qemu.
from 6f398e533f Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-t [...] adds 81c4edc39e tests/tcg: add a multiarch signals test to stress test signa [...] adds 63de93530f meson.build: fix cosmetics of compiler display adds 31fa83bd2b tests/tcg/configure.sh: tweak quoting of target_compiler adds e2ff831462 tests/acceptance: tag various arm tests as TCG only adds b114a0b943 gitlab: work harder to avoid false positives in checkpatch adds e2d3017809 gitlab-ci: Split gprof-gcov job adds 7bb17a9263 tests/vm: expose --source-path to scripts to find extra files adds 72205289a0 scripts/checkpatch.pl: process .c.inc and .h.inc files as C source adds a35947f15c Merge remote-tracking branch 'remotes/stsquad/tags/pull-test [...] adds 0d42cd5c1d target/riscv: Do not include 'pmp.h' in user emulation adds d84451d38e i386/kvm: The value passed to strerror should be positive adds 585190902a misc: Correct relative include path adds 180d4ef3ad linux-user/syscall: Constify bitmask_transtbl fcntl/mmap fla [...] adds d7878875ae docs: fix broken reference adds dd69218949 target/nios2: fix page-fit instruction count adds 69b66e4977 hw/display/macfb: Classify the "nubus-macfb" as display device adds 8daec64be9 target/hppa: Remove unused 'memory.h' header adds 6397856019 target/mips: Fix 'Uncoditional' typo adds eeae5466c4 scripts/oss-fuzz: Fix typo in documentation adds df77d45a51 vhost-vdpa: Remove redundant declaration of address_space_memory adds 33ba8b0adc Merge remote-tracking branch 'remotes/vivier2/tags/trivial-b [...] adds cb53b283b5 hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_ar [...] adds 2cc04550ac hw/riscv: virt: Switch to use qemu_fdt_setprop_string_array( [...] adds 7cfbb17f02 hw/riscv: Support the official CLINT DT bindings adds 60bb5407f0 hw/riscv: Support the official PLIC DT bindings adds 3ede8967c8 docs/system/riscv: Correct the indentation level of supporte [...] adds 0147af69ab docs/system/riscv: sifive_u: Document '-dtb' usage adds a0acd0a175 hw/riscv: Use macros for BIOS image names adds 143897b501 hw/riscv: microchip_pfsoc: Support direct kernel boot adds 719f0f603c target/riscv: fix wfi exception behavior adds 6debd840c8 docs/system: Move the RISC-V -bios information to removed adds bbf3d1b48f target/riscv: Do not include 'pmp.h' in user emulation adds 9a575d33fb target/riscv: Remove unnecessary riscv_*_names[] declaration adds a722701dd3 target/riscv: Dump CSR mscratch/sscratch/satp adds 787a4baf91 target/riscv/pmp: Add assert for ePMP operations adds eee2d61e20 target/riscv: Pass the same value to oprsz and maxsz. adds 00718208c1 target/riscv: reformat @sh format encoding for B-extension adds 438240185a target/riscv: rvb: count leading/trailing zeros adds 1e16310ca1 target/riscv: rvb: count bits set adds 0bcdb686e5 target/riscv: rvb: logic-with-negate adds 6ef5843182 target/riscv: rvb: pack two words into one register adds 82655d8115 target/riscv: rvb: min/max instructions adds 2a81973829 target/riscv: rvb: sign-extend instructions adds 981d3568df target/riscv: add gen_shifti() and gen_shiftiw() helper functions adds 23cd17773b target/riscv: rvb: single-bit instructions adds 91d8fc6768 target/riscv: rvb: shift ones adds e58529a8d0 target/riscv: rvb: rotate (left/right) adds 831ec7f3d1 target/riscv: rvb: generalized reverse adds c24f0422fb target/riscv: rvb: generalized or-combine adds 920a1f9955 target/riscv: rvb: address calculation adds 3a4a43e4e2 target/riscv: rvb: add/shift with prefix zero-extend adds d52e94081e target/riscv: rvb: support and turn on B-extension from comm [...] adds d2c1a177b1 target/riscv: rvb: add b-ext version cpu option adds a4716fd8d7 Merge remote-tracking branch 'remotes/alistair/tags/pull-ris [...]
No new revisions were added by this update.
Summary of changes: .gitlab-ci.d/buildtest.yml | 17 +- .gitlab-ci.d/static_checks.yml | 6 +- docs/system/deprecated.rst | 19 -- docs/system/removed-features.rst | 5 + docs/system/riscv/microchip-icicle-kit.rst | 50 ++- docs/system/riscv/sifive_u.rst | 77 +++-- docs/system/target-riscv.rst | 13 +- hw/display/macfb.c | 1 + hw/gpio/aspeed_gpio.c | 2 +- hw/i386/acpi-common.h | 6 +- hw/i386/kvm/apic.c | 2 +- hw/i386/kvm/clock.c | 4 +- hw/i386/kvm/i8254.c | 10 +- hw/i386/kvm/i8259.c | 4 +- hw/i386/kvm/ioapic.c | 4 +- hw/intc/ppc-uic.c | 2 +- hw/riscv/microchip_pfsoc.c | 81 ++++- hw/riscv/sifive_u.c | 24 +- hw/riscv/spike.c | 12 +- hw/riscv/virt.c | 25 +- hw/virtio/vhost-vdpa.c | 1 + include/exec/memory.h | 2 +- include/hw/riscv/boot.h | 5 + include/hw/virtio/vhost-vdpa.h | 1 - include/monitor/monitor.h | 2 +- linux-user/syscall.c | 4 +- meson.build | 8 +- scripts/checkpatch.pl | 4 +- scripts/oss-fuzz/reorder_fuzzer_qtest_trace.py | 2 +- target/hppa/cpu.h | 1 - target/mips/tcg/translate.c | 6 +- target/nios2/translate.c | 2 +- target/riscv/bitmanip_helper.c | 90 +++++ target/riscv/cpu.c | 38 ++- target/riscv/cpu.h | 9 +- target/riscv/cpu_bits.h | 1 + target/riscv/helper.h | 6 + target/riscv/insn32.decode | 87 ++++- target/riscv/insn_trans/trans_rvb.c.inc | 438 +++++++++++++++++++++++++ target/riscv/insn_trans/trans_rvi.c.inc | 54 +-- target/riscv/insn_trans/trans_rvv.c.inc | 89 ++--- target/riscv/meson.build | 1 + target/riscv/op_helper.c | 11 +- target/riscv/pmp.c | 4 + target/riscv/translate.c | 306 +++++++++++++++++ tests/acceptance/boot_linux_console.py | 18 + tests/tcg/configure.sh | 6 +- tests/tcg/multiarch/Makefile.target | 2 + tests/tcg/multiarch/signals.c | 149 +++++++++ tests/vm/Makefile.include | 1 + tests/vm/basevm.py | 4 + tests/vm/centos.aarch64 | 2 +- 52 files changed, 1491 insertions(+), 227 deletions(-) create mode 100644 target/riscv/bitmanip_helper.c create mode 100644 target/riscv/insn_trans/trans_rvb.c.inc create mode 100644 tests/tcg/multiarch/signals.c