[Tcwg-commits] [llvm] branch master updated (30bc60c9e3b -> 700e61c5aa9)

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from 30bc60c9e3b [X86][AVX] Tweak X86ISD::VPERMV3 demandedelts test new 700e61c5aa9 [RISCV] Diagnose invalid second input register operand when [...]

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Summary of changes: lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp | 28 +++++++++++++++++++++++++-- test/MC/RISCV/rv32i-invalid.s | 1 + 2 files changed, 27 insertions(+), 2 deletions(-)