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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-next-defconfig in repository toolchain/ci/llvm-project.
from 9a05547954a [AArch64] Precommit tests for D77316 adds 6211830fbab [VectorCombine] add reduction-like patterns; NFC adds 2123bb843e4 [ARM] Patterns for VQSHRN adds 604f44977bd [InstCombine] Clean up alignment handling (NFC) adds 43017ceb784 [PhaseOrdering] add vector reduction tests; NFC adds 81e9ede3a2d [VectorCombine] forward walk through instructions to improv [...] adds 49c9a68d7fc The release notes for ObjCBreakBeforeNestedBlockParam was p [...] adds 32870a84d9a Expose IRGen API to add the default IR attributes to a func [...]
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Summary of changes: clang/docs/ReleaseNotes.rst | 32 ++--- clang/include/clang/CodeGen/CodeGenABITypes.h | 20 +++ clang/lib/CodeGen/CGCall.cpp | 141 ++++++++++++++------- clang/lib/CodeGen/CodeGenABITypes.cpp | 5 + clang/lib/CodeGen/CodeGenAction.cpp | 2 +- clang/lib/CodeGen/CodeGenModule.h | 17 ++- llvm/lib/Target/ARM/ARMInstrMVE.td | 18 +++ .../InstCombine/InstCombineLoadStoreAlloca.cpp | 33 +---- llvm/lib/Transforms/Vectorize/VectorCombine.cpp | 5 +- llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll | 78 ++++-------- llvm/test/CodeGen/Thumb2/mve-vqshrn.ll | 24 ++-- .../PhaseOrdering/X86/vector-reductions.ll | 69 ++++++++++ .../Transforms/VectorCombine/X86/extract-binop.ll | 61 +++++++++ .../Transforms/VectorCombine/X86/insert-binop.ll | 8 +- 14 files changed, 336 insertions(+), 177 deletions(-) create mode 100644 llvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll