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from 9ec5d6de735 Revert "Fix type error of 'switch (SUBREG_BYTE (op)).'" new 17c22f46616 RISC-V: Minimal support for ZC* extensions. new 6e46fcdf24f RISC-V: Enable compressible features when use ZC* extensions. new 7879f589af9 RISC-V: Add ZC* test for failed march args being passed.
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Summary of changes: gcc/common/config/riscv/riscv-common.cc | 38 +++++++++++++++++++++++++++++++ gcc/config/riscv/riscv-c.cc | 2 +- gcc/config/riscv/riscv-opts.h | 16 +++++++++++++ gcc/config/riscv/riscv-shorten-memrefs.cc | 3 ++- gcc/config/riscv/riscv.cc | 11 +++++---- gcc/config/riscv/riscv.h | 2 +- gcc/config/riscv/riscv.opt | 3 +++ gcc/testsuite/gcc.target/riscv/arch-24.c | 5 ++++ gcc/testsuite/gcc.target/riscv/arch-25.c | 5 ++++ 9 files changed, 78 insertions(+), 7 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/arch-24.c create mode 100644 gcc/testsuite/gcc.target/riscv/arch-25.c