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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_check/master-aarch64 in repository toolchain/ci/gcc.
from 527a1cf32c2 testsuite/lib/gfortran.exp: Add -I for ISO*.h [PR101305, PR101660] adds 2eff2a3cb52 libstdc++: Make allocator equality comparable in tests adds 848bcda52d7 Improve handling of unknown sign bit in CCP. adds 67b8443bd1f [documentation] Fix GTY header file example adds 7cc85851bc7 [documentation] No need anymore to "mention ['gt-*.h' file] [...] adds 06870af3e48 [OpenACC] Clean up unused 'BUILT_IN_ACC_GET_DEVICE_TYPE' adds c5230519305 Sanity check that 'Init' doesn't appear without 'Var' in '* [...] adds 2a700fb8ea9 Don't consider '-foffload-abi' in 'DEF_GOACC_BUILTIN', 'DEF [...] adds 0095afa82a3 Remove 'gcc/omp-offload.c' from 'GTFILES' adds e2e0b85c1e7 PR101609: Use the correct iterator for AArch64 vector right [...]
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Summary of changes: gcc/Makefile.in | 1 - gcc/builtins.def | 8 +- gcc/common.opt | 2 +- gcc/config/aarch64/aarch64-simd.md | 15 ++- gcc/doc/gty.texi | 5 +- gcc/omp-builtins.def | 2 - gcc/optc-gen.awk | 8 +- gcc/opts.c | 6 +- gcc/testsuite/g++.dg/ipa/pure-const-3.C | 2 +- gcc/testsuite/gcc.dg/pr68217.c | 2 +- gcc/testsuite/gcc.dg/tree-ssa/vrp24.c | 2 +- .../gcc.target/aarch64/vect-shr-reg-run.c | 53 +++++++++ gcc/testsuite/gcc.target/aarch64/vect-shr-reg.c | 30 ++++++ gcc/tree-ssa-ccp.c | 118 ++++++++++++++++++--- .../23_containers/unordered_map/cons/default.cc | 3 + .../23_containers/unordered_set/cons/default.cc | 3 + 16 files changed, 217 insertions(+), 43 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/vect-shr-reg-run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/vect-shr-reg.c