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from 7c5761290de [FastISel] Copy the inline assembly dialect to the INLINEAS [...] new 1c6d4fc3e0b AMDGPU/GlobalISel: Fix RegBankSelect for sendmsg intrinsics new 97454bf24b5 GlobalISel: Partially implement lower for G_EXTRACT new 9ab5b297df5 AMDGPU/GlobalISel: Lower G_ATOMIC_CMPXCHG_WITH_SUCCESS new c8e8fe1934e AMDGPU/GlobalISel: RegBankSelect DS GWS intrinsics new df6dd00906a AMDGPU/GlobalISel: RegBankSelect mul24 intrinsics new 062bcee3891 AMDGPU/GlobalISel: Fall back on weird G_EXTRACT offsets
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Summary of changes: include/llvm/CodeGen/GlobalISel/LegalizerHelper.h | 1 + lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 35 ++++ lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp | 7 +- lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 17 +- lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 48 +++++- .../GlobalISel/artifact-combiner-extract.mir | 14 +- .../legalize-atomic-cmpxchg-with-success.mir | 107 ++++++++++++ .../GlobalISel/legalize-extract-vector-elt.mir | 20 ++- .../CodeGen/AMDGPU/GlobalISel/legalize-extract.mir | 183 ++++++++++++++++++++- .../AMDGPU/GlobalISel/legalize-shuffle-vector.mir | 20 ++- .../regbankselect-amdgcn.ds.gws.init.mir | 79 +++++++++ .../regbankselect-amdgcn.ds.gws.sema.v.mir | 37 +++++ .../GlobalISel/regbankselect-amdgcn.s.sendmsg.mir | 13 +- .../regbankselect-amdgcn.s.sendmsghalt.mir | 15 +- .../AMDGPU/GlobalISel/regbankselect-constant.mir | 8 +- 15 files changed, 546 insertions(+), 58 deletions(-) create mode 100644 test/CodeGen/AMDGPU/GlobalISel/legalize-atomic-cmpxchg-with-suc [...] create mode 100644 test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.init.mir create mode 100644 test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.sema.v.mir