This is an automated email from the git hooks/post-receive script.
tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_cross/gnu-master-aarch64-build_cross in repository toolchain/ci/gcc.
from 4d3eaeb4f50 libstdc++: Simplify basic_string_view::ends_with [PR 101361] adds acd4b9103c1 rs6000: Add support for SSE4.1 "test" intrinsics adds 60aee15bb7e rs6000: Add tests for SSE4.1 "test" intrinsics adds 8695bf78dad gcc: Add vec_select -> subreg RTL simplification adds 0e7754560f6 Daily bump. adds 66907e73995 adjust landing pads when changing main label adds a7098d6ef4e fix typo in attr_fnspec::verify new 1dd3f210958 Support reduction def re-use for epilogue with different ve [...]
The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.
Summary of changes: gcc/ChangeLog | 186 ++++++++++++ gcc/DATESTAMP | 2 +- gcc/combine.c | 14 + gcc/config/aarch64/aarch64.md | 11 +- gcc/config/arm/vfp.md | 2 +- gcc/config/rs6000/smmintrin.h | 56 ++++ gcc/cse.c | 14 + gcc/rtl.c | 15 + gcc/rtl.h | 1 + gcc/rtlanal.c | 19 ++ gcc/rtlanal.h | 3 + gcc/simplify-rtx.c | 10 + gcc/testsuite/ChangeLog | 157 +++++++++++ .../gcc.target/aarch64/extract_zero_extend.c | 9 - .../gcc.target/aarch64/narrow_high_combine.c | 314 ++++++++++++++------- .../gcc.target/aarch64/simd/vmulx_laneq_f64_1.c | 2 +- .../gcc.target/aarch64/simd/vmulxd_laneq_f64_1.c | 2 +- .../gcc.target/aarch64/simd/vmulxs_lane_f32_1.c | 2 +- .../gcc.target/aarch64/simd/vmulxs_laneq_f32_1.c | 2 +- .../gcc.target/aarch64/simd/vqdmlalh_lane_s16.c | 2 +- .../gcc.target/aarch64/simd/vqdmlals_lane_s32.c | 2 +- .../gcc.target/aarch64/simd/vqdmlslh_lane_s16.c | 2 +- .../gcc.target/aarch64/simd/vqdmlsls_lane_s32.c | 2 +- .../gcc.target/aarch64/simd/vqdmullh_lane_s16.c | 2 +- .../gcc.target/aarch64/simd/vqdmullh_laneq_s16.c | 2 +- .../gcc.target/aarch64/simd/vqdmulls_lane_s32.c | 2 +- .../gcc.target/aarch64/simd/vqdmulls_laneq_s32.c | 2 +- gcc/testsuite/gcc.target/aarch64/sve/dup_lane_1.c | 20 +- gcc/testsuite/gcc.target/aarch64/sve/extract_1.c | 4 +- gcc/testsuite/gcc.target/aarch64/sve/extract_2.c | 4 +- gcc/testsuite/gcc.target/aarch64/sve/extract_3.c | 4 +- gcc/testsuite/gcc.target/aarch64/sve/extract_4.c | 4 +- gcc/testsuite/gcc.target/aarch64/sve/live_1.c | 5 +- gcc/testsuite/gcc.target/arm/crypto-vsha1cq_u32.c | 4 +- gcc/testsuite/gcc.target/arm/crypto-vsha1h_u32.c | 4 +- gcc/testsuite/gcc.target/arm/crypto-vsha1mq_u32.c | 4 +- gcc/testsuite/gcc.target/arm/crypto-vsha1pq_u32.c | 4 +- .../gcc.target/arm/mve/intrinsics/vgetq_lane_f16.c | 4 +- .../gcc.target/arm/mve/intrinsics/vgetq_lane_f32.c | 4 +- .../gcc.target/arm/mve/intrinsics/vgetq_lane_s16.c | 4 +- .../gcc.target/arm/mve/intrinsics/vgetq_lane_s32.c | 4 +- .../gcc.target/arm/mve/intrinsics/vgetq_lane_s8.c | 4 +- .../gcc.target/arm/mve/intrinsics/vgetq_lane_u16.c | 4 +- .../gcc.target/arm/mve/intrinsics/vgetq_lane_u32.c | 4 +- .../gcc.target/arm/mve/intrinsics/vgetq_lane_u8.c | 4 +- gcc/testsuite/gcc.target/i386/vect-reduc-1.c | 17 ++ gcc/testsuite/gcc.target/powerpc/sse4_1-ptest-1.c | 117 ++++++++ gcc/tree-cfg.c | 6 +- gcc/tree-ssa-alias.c | 2 +- gcc/tree-vect-loop.c | 227 +++++++++------ libgomp/ChangeLog | 7 + libstdc++-v3/ChangeLog | 11 + 52 files changed, 1052 insertions(+), 261 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/vect-reduc-1.c create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-ptest-1.c