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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-next-allyesconfig in repository toolchain/ci/llvm-project.
from 57d8b8d6f0b [openmp] Fixed hang if detached task was serialized. adds 79f059c4ac8 [mlir] NFC - Fix OperationSupport.cpp::findNamedAttr adds 03092f2fa7b [mlir] Add BoolArrayAttr in Tablegen + Builder support adds 5b0502dff5b [pstl] A fix for move placement-new (and destroy) allocated [...] adds 22d40cc3a72 [Analyzer][StreamChecker] Changed representation of stream [...] adds 1907f28b47c [Analyzer][StreamChecker] Fixed compile error - NFC. adds 10e2e7de0c0 [WebAssembly] iterate stack in DebugFixup from the top. adds 364c595403c [SVE] Ignore scalable vectors in InterleavedLoadCombinePass adds 36cdc17f8cf [mlir][Vector] Make minor identity permutation map optional [...] adds 1870e787af9 [mlir][Vector] Add an optional "masked" boolean array attri [...] adds 681a161ff54 AMDGPU: Remove outdated comment adds 4c70074e543 AMDGPU/GlobalISel: Fix splitting wide VALU, non-vector loads adds d1866f89472 [MLIR] [Linalg] Add option to use the partial view after pr [...] adds a4cb9bec1ca [mlir] Support optional attributes in assembly formats adds 23dc948d362 [MLIR] Use `MLIR_INCLUDE_TESTS` to conditionally compile tests. adds 623b2542446 [Local] Do not ignore zexts in salvageDebugInfo, PR45923 adds 2084330e41d [lldb/Reproducers] Add skipIfReproducer to more tests adds 691980ebb47 [llvm][NFC] Fixed non-compliant style in InlineAdvisor.h adds 31ecef76275 [SystemZ] Don't create PERMUTE nodes with an undef operand. adds bdd8c111fc0 [IR] Revert r2694 in BasicBlock::removePredecessor adds a7cc275e7e8 Add verifier check that musttail and preallocated are not u [...] adds b7924d6525b [dsymutil] Make sure the --help output and man page are consistent adds 3c4ef745557 Fixed a typo in the comment for allocateBuffer() adds 736db2f7103 [Loads] Require Align in isSafeToLoadUnconditionally() (NFC) adds 63081dc6f64 LoadStoreVectorizer: Match nested adds to prove vectorizati [...] adds bf527a1dc41 AMDGPU/GlobalISel: Fix f64 G_FDIV lowering adds 715b7d8aa5d [mlir][vulkan-runner] Add back accidentially removed header [...] adds ef649e8fd5d Revert "[CUDA][HIP] Workaround for resolving host device fu [...] adds b27a538dda4 AMDGPU: Fix illegally constant folding from V_MOV_B32_sdwa adds cd12e79e6dd [x86] Propagate memory operands during ISel DAG postprocessing adds 3f5f8f39734 [compiler-rt][CMake] Fix PowerPC runtime build
No new revisions were added by this update.
Summary of changes: clang/include/clang/Sema/Sema.h | 2 - clang/lib/Sema/SemaCUDA.cpp | 14 - clang/lib/Sema/SemaOverload.cpp | 143 +++------ .../lib/StaticAnalyzer/Checkers/StreamChecker.cpp | 252 +++++++-------- clang/test/SemaCUDA/function-overload.cu | 146 +-------- compiler-rt/cmake/base-config-ix.cmake | 3 +- .../step_over_breakpoint/TestStepOverBreakpoint.py | 1 + .../deleted-executable/TestDeletedExecutable.py | 1 + .../functionalities/load_unload/TestLoadUnload.py | 1 + .../postmortem/elf-core/TestLinuxCore.py | 12 + .../postmortem/netbsd-core/TestNetBSDCore.py | 6 + llvm/docs/CommandGuide/dsymutil.rst | 34 +-- llvm/include/llvm/Analysis/InlineAdvisor.h | 6 +- llvm/include/llvm/Analysis/Loads.h | 4 +- llvm/lib/Analysis/Loads.cpp | 21 +- llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp | 17 +- llvm/lib/IR/BasicBlock.cpp | 18 +- llvm/lib/IR/Verifier.cpp | 3 + llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 2 +- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 15 +- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 7 - llvm/lib/Target/AMDGPU/VOP1Instructions.td | 11 +- llvm/lib/Target/SystemZ/SystemZISelLowering.cpp | 3 +- .../Target/WebAssembly/WebAssemblyDebugFixup.cpp | 5 +- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 2 + llvm/lib/Transforms/IPO/Inliner.cpp | 6 +- llvm/lib/Transforms/Scalar/SROA.cpp | 8 +- .../Transforms/Scalar/TailRecursionElimination.cpp | 2 +- llvm/lib/Transforms/Utils/Local.cpp | 9 +- .../Transforms/Vectorize/LoadStoreVectorizer.cpp | 70 ++++- .../CodeGen/AMDGPU/GlobalISel/legalize-fdiv.mir | 340 ++++++--------------- .../AMDGPU/GlobalISel/regbankselect-load.mir | 320 ++++++++++++------- .../AMDGPU/atomic_optimizations_local_pointer.ll | 22 +- .../AMDGPU/atomic_optimizations_pixelshader.ll | 4 +- .../CodeGen/AMDGPU/constant-fold-imm-immreg.mir | 30 ++ llvm/test/CodeGen/SystemZ/vec-perm-14.ll | 27 ++ .../SystemZ/vector-constrained-fp-intrinsics.ll | 6 +- .../X86/isel-postprocessing-test-fold-memop.ll | 14 + .../test/Transforms/InstCombine/cast-mul-select.ll | 6 +- .../X86/vectorize-i8-nested-add.ll | 165 ++++++++++ llvm/test/Verifier/preallocated-invalid.ll | 7 + llvm/test/tools/dsymutil/cmdline.test | 54 ++-- llvm/tools/dsymutil/Options.td | 3 +- mlir/CMakeLists.txt | 11 +- .../mlir/Dialect/Linalg/Transforms/Transforms.h | 23 ++ mlir/include/mlir/Dialect/Vector/EDSC/Intrinsics.h | 3 + mlir/include/mlir/Dialect/Vector/VectorOps.h | 9 + mlir/include/mlir/Dialect/Vector/VectorOps.td | 141 ++++++--- mlir/include/mlir/IR/Builders.h | 1 + mlir/include/mlir/IR/OpBase.td | 4 + .../Conversion/StandardToLLVM/StandardToLLVM.cpp | 2 +- .../VectorToLLVM/ConvertVectorToLLVM.cpp | 69 +++-- mlir/lib/Conversion/VectorToSCF/VectorToSCF.cpp | 65 ++-- .../Dialect/Affine/Transforms/SuperVectorize.cpp | 8 +- mlir/lib/Dialect/Linalg/Transforms/Promotion.cpp | 30 +- mlir/lib/Dialect/Vector/VectorOps.cpp | 169 ++++++++-- mlir/lib/Dialect/Vector/VectorTransforms.cpp | 10 +- mlir/lib/IR/Builders.cpp | 7 +- mlir/lib/IR/OperationSupport.cpp | 2 +- .../AffineToStandard/lower-affine-to-vector.mlir | 18 +- .../Conversion/VectorToLLVM/vector-to-llvm.mlir | 18 ++ .../Conversion/VectorToLoops/vector-to-loops.mlir | 35 ++- .../Affine/SuperVectorize/vectorize_1d.mlir | 47 ++- .../Affine/SuperVectorize/vectorize_2d.mlir | 20 +- .../Affine/SuperVectorize/vectorize_3d.mlir | 2 +- mlir/test/Dialect/Linalg/promote.mlir | 15 +- mlir/test/Dialect/Vector/invalid.mlir | 69 ++++- mlir/test/Dialect/Vector/ops.mlir | 8 +- mlir/test/Dialect/Vector/vector-transforms.mlir | 32 +- mlir/test/lib/Dialect/Test/TestOps.td | 8 +- mlir/test/lib/Transforms/TestLinalgTransforms.cpp | 16 +- mlir/test/mlir-tblgen/op-format.mlir | 7 + mlir/tools/mlir-opt/CMakeLists.txt | 18 +- mlir/tools/mlir-opt/mlir-opt.cpp | 4 + mlir/tools/mlir-tblgen/OpFormatGen.cpp | 10 +- mlir/tools/mlir-vulkan-runner/CMakeLists.txt | 5 + pstl/include/pstl/internal/algorithm_impl.h | 120 ++++++-- pstl/include/pstl/internal/memory_impl.h | 67 +++- .../include/pstl/internal/parallel_backend_utils.h | 118 +++++++ .../algorithms/alg.merge/inplace_merge.pass.cpp | 7 + .../alg.modifying.operations/remove.pass.cpp | 7 + .../alg.modifying.operations/rotate.pass.cpp | 3 + .../alg.modifying.operations/unique.pass.cpp | 6 + .../alg.sorting/alg.set.operations/set.pass.cpp | 151 ++++++++- .../alg.sorting/partial_sort_copy.pass.cpp | 5 + pstl/test/support/utils.h | 76 +++++ 86 files changed, 2080 insertions(+), 1188 deletions(-) create mode 100644 llvm/test/CodeGen/SystemZ/vec-perm-14.ll create mode 100644 llvm/test/CodeGen/X86/isel-postprocessing-test-fold-memop.ll create mode 100644 llvm/test/Transforms/LoadStoreVectorizer/X86/vectorize-i8-neste [...]