This is an automated email from the git hooks/post-receive script.
tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-stable-allnoconfig in repository toolchain/ci/qemu.
from 3757b0d08b Merge tag 'pull-request-2022-05-18' of https://gitlab.com/th [...] adds d6cd3ae0eb target/riscv: Fix VS mode hypervisor CSR access adds 02b511985e target/riscv: rvv: Fix early exit condition for whole regist [...] adds 77046729f9 hw/intc: Pass correct hartid while updating mtimecmp adds 6047dcc245 target/riscv: Move Zhinx* extensions on ISA string adds a4a9a4432e target/riscv: Add short-isa-string option adds 4bcfc391ac hw/riscv: Make CPU config error handling generous (virt/spike) adds 91a3387dc4 hw/riscv: Make CPU config error handling generous (sifive_e/ [...] adds 61cdf4593e target/riscv: Fix coding style on "G" expansion adds 1d398ab9dc target/riscv: Disable "G" by default adds 9f6b7da5d2 target/riscv: Change "G" expansion adds 1086504c6f target/riscv: FP extension requirements adds bc57381669 target/riscv: Move/refactor ISA extension checks adds 8f1b608798 hw/vfio/pci-quirks: Resolve redundant property getters adds 96c7fff703 hw/riscv/sifive_u: Resolve redundant property accessors adds bb06941f95 target/riscv: check 'I' and 'E' after checking 'G' in riscv_ [...] adds 075eeda931 target/riscv: Fix typo of mimpid cpu option adds c1fbcecb3a target/riscv: Fix csr number based privilege checking adds 24826da0ee target/riscv: Fix hstatus.GVA bit setting for traps taken fr [...] adds 62cf02451e target/riscv: Set [m|s]tval for both illegal and virtual ins [...] adds d644e5e44f hw/riscv: virt: Fix interrupt parent for dynamic platform devices adds 5160bacc06 target/riscv: add zicsr/zifencei to isa_string adds d616889ece hw/core: Sync uboot_image.h from U-Boot v2022.01 adds 8fe63fe8e5 hw/core: loader: Set is_linux to true for VxWorks uImage adds 0cac736e73 Merge tag 'pull-riscv-to-apply-20220525' of github.com:alist [...]
No new revisions were added by this update.
Summary of changes: hw/core/loader.c | 15 +++ hw/core/uboot_image.h | 213 +++++++++++++++++++++----------- hw/intc/riscv_aclint.c | 3 +- hw/riscv/opentitan.c | 2 +- hw/riscv/sifive_e.c | 2 +- hw/riscv/sifive_u.c | 28 +---- hw/riscv/spike.c | 2 +- hw/riscv/virt.c | 27 ++-- hw/vfio/pci-quirks.c | 34 ++--- target/riscv/cpu.c | 91 ++++++++++---- target/riscv/cpu.h | 12 +- target/riscv/cpu_helper.c | 4 +- target/riscv/csr.c | 26 ++-- target/riscv/insn_trans/trans_rvv.c.inc | 58 +++++---- target/riscv/translate.c | 17 ++- 15 files changed, 325 insertions(+), 209 deletions(-)