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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-next-allmodconfig in repository toolchain/ci/llvm-project.
from 6283d2aa519 Revert "[LLDB] Unbreak the build after recent clang changes" adds a5311d731e1 [clang-tidy] Handle template instantiations in container si [...] adds ae8f4b2178c [AMDGPU] Folding of FI operand with flat scratch adds 333108e8bef Add a llvm.coro.end.async intrinsic adds 9cb748724ef [OpenMP][Docs] Add FAQ entry about math and complex on GPUs adds 1eb082c2ea4 [OpenMP][Docs] Fixed a typo in the doc that can mislead use [...] adds 7b0f9dd79a3 [OpenMP][Docs] Fix Typo adds 53deef9e0b8 [RISCV] Remove unneeded !eq comparing a single bit value to [...] adds 7ec7788ac17 Try to fix build on Windows adds 57ffbe020af glld/mac] Don't add names of unreferenced symbols to string table adds 0d15d4b6f43 [SLP] use operand index abstraction for number of operands adds f6929c01952 [SLP] add reduction tests for maxnum/minnum intrinsics; NFC adds 3dbe471a260 [clangd] Use atomics instead of locks to track periodic mem [...] adds df6cbd37f57 [mlir] Lower gpu.memcpy to GPU runtime calls. adds f7a26127f21 [clangd] Release notes for b8c37153d5393aad96 adds a781a706b96 [WebAssembly][SIMD] Rename shuffle, swizzle, and load_splats adds 8de43b926f0 [mlir] Remove instance methods from LLVMType adds 1c19804ebf4 [OpenMP] Add OpenMP Documentation for Libomptarget environm [...] adds 75a3f326c3d [IR] Add an ImplicitLocOpBuilder helper class for building [...] adds 6dfe5801e01 scudo: Move the configuration for the primary allocator to [...] adds ca4bf58e4ee [AMDGPU] Support unaligned flat scratch in TLI adds d15119a02d9 [AMDGPU][GlobalISel] GlobalISel for flat scratch adds e6b3db6309f scudo: Replace the Cache argument on MapAllocator with a Co [...] adds faac1c02c80 scudo: Move the management of the UseMemoryTagging bit out [...] adds 22cf54a7fba Replace `T(x)` with `reinterpret_cast<T>(x)` everywhere it [...] adds 5bec0828347 VirtRegMap: Use Register adds 29ed846d671 AMDGPU: Fix assert when checking for implicit operand legality adds c8874464b5f [RISCV] Add intrinsics for vslide1up/down, vfslide1up/down [...] adds 42687839980 [RISCV] Add intrinsics for vwmacc[u|su|us] instructions adds ad0a7ad950f [RISCV] Add intrinsics for vf[n]macc/vf[n]msac/vf[n]madd/vf [...] adds bac54639c7b AMDGPU: Add spilled CSR SGPRs to entry block live ins adds 8bf9cdeaee4 AMDGPU: Use Register adds 77fb45e59e4 [lld/mac] Add --version flag adds 581d13f8aeb GlobalISel: Return APInt from getConstantVRegVal adds e6fde1ae7df [MemorySSA] Use is_contained (NFC) adds efe7f5ede0b [WebAssembly][NFC] Refactor SIMD load/store tablegen defs adds 3c707d73f26 [NewGVN] Remove for_each_found (NFC) adds 0219cf7dfaf [NewPM] Fix objc-arc-apelim pass typo adds 4d479443934 [RISCV] Define the vfmin, vfmax RVV intrinsics adds 032600b9aef [RISCV] Define vmerge/vfmerge intrinsics. adds bdef1f87aba [llvm-readobj] - Dump the ELF file type better. adds 6301871d06d [RISCV] Add intrinsics for vfwmacc, vfwnmacc, vfwmsac, vfwn [...] adds 221fdedc692 [AMDGPU][GlobalISel] Fold flat vgpr + constant addresses adds 65ba0cd3955 [mlir] Modernize std-to-llvm operation conversion doc adds 8451d4872ed [mlir] NFC: Remove ConvertToLLVMPattern::getDataPtr(). All [...] adds 32a884c9c52 [mlir] Add translation of omp.wsloop to LLVM IR adds 19a0d0a40ce [mlir] Rename ConvertToLLVMPattern::isSupportedMemRefType() [...] adds 25a02c3d1a6 Revert "PR24076, PR33655, C++ CWG 1558: Consider the instan [...] adds eb9483b2105 [format] Add overload to parseConfiguration that accept llv [...] adds 7ed9cfc7b19 [mlir] Remove static constructors from LLVMType adds c3acda0798f [VE] Vector 'and' isel and tests adds acaa6e4260c [NFC] Uniquify 'const' in TargetTransformInfoImpl.h adds a9f14cdc620 [ARM] Add bank conflict hazarding adds 6e603464959 [OpenMP] Fixing Typo in Documentation adds 5426b2f9ed9 [clang-format] PR48535 clang-format Incorrectly Removes Spa [...] adds 031743cb5b3 [clang-format] PR48539 ReflowComments breaks Qt translation [...] adds 1d0dc9be6d7 [MLIR][SPIRV] Add rewrite pattern to convert select+cmp int [...] adds 2522fa053b6 [clangd] Do not take stale definition from the static index. adds 9fb074e7bb1 [BPI] Improve static heuristics for "cold" paths. adds e122a71a0a2 [TableGen] Add the !substr() bang operator adds 9d1140e18e6 [lld-macho] Simulator & DriverKit executables should always be PIE adds 631501b1f90 [OpenMP] Fixing typo on memory size in Documenation adds 7ad666798f1 Revert 741978d727 and things that landed on top of it. adds 42980a789d2 [mlir][spirv] Convert functions returning one value
No new revisions were added by this update.
Summary of changes: .../readability/ContainerSizeEmptyCheck.cpp | 183 ++- clang-tools-extra/clangd/ClangdLSPServer.cpp | 37 +- clang-tools-extra/clangd/ClangdLSPServer.h | 11 +- clang-tools-extra/clangd/index/Merge.cpp | 6 + clang-tools-extra/clangd/support/Threading.cpp | 12 + clang-tools-extra/clangd/support/Threading.h | 29 + clang-tools-extra/clangd/unittests/IndexTests.cpp | 34 + .../clangd/unittests/support/ThreadingTests.cpp | 21 + clang-tools-extra/docs/ReleaseNotes.rst | 12 +- .../checkers/readability-container-size-empty.cpp | 218 ++- clang/include/clang/AST/Type.h | 4 +- clang/include/clang/Basic/CodeGenOptions.h | 2 - clang/include/clang/Basic/DiagnosticDriverKinds.td | 2 + .../include/clang/Basic/DiagnosticFrontendKinds.td | 2 + clang/include/clang/Driver/Options.td | 1357 ++++++---------- clang/include/clang/Format/Format.h | 13 +- clang/lib/AST/ItaniumMangle.cpp | 4 - clang/lib/CodeGen/CGCall.h | 6 +- clang/lib/Format/BreakableToken.cpp | 4 +- clang/lib/Format/Format.cpp | 16 +- clang/lib/Format/TokenAnnotator.cpp | 7 + clang/lib/Frontend/CompilerInvocation.cpp | 806 +++++++++- clang/test/CXX/drs/dr15xx.cpp | 14 - clang/test/CodeGenCXX/mangle-template.cpp | 20 - clang/test/Format/error-config.cpp | 4 +- clang/test/Profile/c-generate.c | 2 +- .../test/SemaTemplate/instantiation-dependence.cpp | 74 - .../test/SemaTemplate/partial-spec-instantiate.cpp | 18 +- clang/unittests/Format/FormatTest.cpp | 14 + clang/unittests/Format/FormatTestComments.cpp | 6 + clang/www/cxx_dr_status.html | 2 +- .../lib/scudo/standalone/allocator_config.h | 51 +- compiler-rt/lib/scudo/standalone/combined.h | 32 +- compiler-rt/lib/scudo/standalone/memtag.h | 5 + compiler-rt/lib/scudo/standalone/options.h | 6 + compiler-rt/lib/scudo/standalone/primary32.h | 32 +- compiler-rt/lib/scudo/standalone/primary64.h | 35 +- compiler-rt/lib/scudo/standalone/secondary.h | 14 +- .../lib/scudo/standalone/tests/combined_test.cpp | 25 +- .../lib/scudo/standalone/tests/primary_test.cpp | 62 +- .../lib/scudo/standalone/tests/secondary_test.cpp | 20 +- lld/COFF/Options.td | 2 +- lld/MachO/Driver.cpp | 40 +- lld/MachO/Options.td | 4 +- lld/MachO/SyntheticSections.cpp | 22 +- lld/test/MachO/driver.test | 4 +- lld/test/MachO/platform-version.s | 2 +- lld/test/MachO/symtab.s | 6 +- lld/test/MachO/x86-64-reloc-unsigned.s | 4 + llvm/docs/Coroutines.rst | 42 + llvm/docs/TableGen/ProgRef.rst | 10 +- llvm/include/llvm/Analysis/BranchProbabilityInfo.h | 153 +- .../llvm/Analysis/LazyBranchProbabilityInfo.h | 2 +- .../llvm/Analysis/TargetTransformInfoImpl.h | 196 ++- .../llvm/CodeGen/GlobalISel/MIPatternMatch.h | 2 +- llvm/include/llvm/CodeGen/GlobalISel/Utils.h | 11 +- llvm/include/llvm/CodeGen/VirtRegMap.h | 8 +- llvm/include/llvm/IR/Intrinsics.td | 2 + llvm/include/llvm/IR/IntrinsicsRISCV.td | 51 +- llvm/include/llvm/IR/SymbolTableListTraits.h | 8 +- llvm/include/llvm/Object/Binary.h | 4 +- llvm/include/llvm/Option/OptParser.td | 9 +- llvm/include/llvm/TableGen/Record.h | 2 +- llvm/lib/Analysis/BranchProbabilityInfo.cpp | 645 ++++---- llvm/lib/Analysis/MemorySSA.cpp | 3 +- llvm/lib/Analysis/OptimizationRemarkEmitter.cpp | 2 +- llvm/lib/CodeGen/AsmPrinter/OcamlGCPrinter.cpp | 7 +- llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp | 28 +- .../lib/CodeGen/GlobalISel/InstructionSelector.cpp | 2 +- llvm/lib/CodeGen/GlobalISel/Utils.cpp | 30 +- llvm/lib/CodeGen/LiveRangeEdit.cpp | 2 +- llvm/lib/Object/COFFObjectFile.cpp | 24 +- llvm/lib/Object/ELFObjectFile.cpp | 3 +- llvm/lib/Object/XCOFFObjectFile.cpp | 4 +- llvm/lib/Passes/PassRegistry.def | 2 +- llvm/lib/TableGen/Record.cpp | 28 +- llvm/lib/TableGen/TGLexer.cpp | 1 + llvm/lib/TableGen/TGLexer.h | 6 +- llvm/lib/TableGen/TGParser.cpp | 95 +- llvm/lib/TableGen/TGParser.h | 1 + .../AArch64/GISel/AArch64InstructionSelector.cpp | 47 +- .../Target/AArch64/GISel/AArch64LegalizerInfo.cpp | 2 +- .../AArch64/GISel/AArch64PostLegalizerCombiner.cpp | 2 +- .../AArch64/GISel/AArch64PostLegalizerLowering.cpp | 2 +- llvm/lib/Target/AMDGPU/AMDGPUGISel.td | 8 + .../Target/AMDGPU/AMDGPUInstructionSelector.cpp | 97 +- llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h | 3 + llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 26 +- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 2 +- llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp | 8 +- llvm/lib/Target/AMDGPU/SIFoldOperands.cpp | 57 +- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 15 +- llvm/lib/Target/AMDGPU/SIInstrInfo.h | 3 + llvm/lib/Target/AMDGPU/SIInstrInfo.td | 7 + llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp | 19 +- llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 4 + llvm/lib/Target/ARM/ARM.td | 4 +- llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 25 + llvm/lib/Target/ARM/ARMBaseInstrInfo.h | 4 + llvm/lib/Target/ARM/ARMHazardRecognizer.cpp | 173 ++ llvm/lib/Target/ARM/ARMHazardRecognizer.h | 32 + llvm/lib/Target/ARM/ARMSubtarget.cpp | 1 + llvm/lib/Target/ARM/ARMSubtarget.h | 2 + llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp | 9 +- llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td | 242 ++- llvm/lib/Target/VE/VVPInstrInfo.td | 3 + llvm/lib/Target/VE/VVPInstrPatternsVec.td | 3 + llvm/lib/Target/VE/VVPNodes.def | 1 + .../MCTargetDesc/WebAssemblyMCTargetDesc.h | 40 +- .../lib/Target/WebAssembly/WebAssemblyInstrSIMD.td | 322 ++-- llvm/lib/Target/X86/X86InstructionSelector.cpp | 2 +- llvm/lib/Transforms/Coroutines/CoroEarly.cpp | 7 +- llvm/lib/Transforms/Coroutines/CoroFrame.cpp | 19 +- llvm/lib/Transforms/Coroutines/CoroInstr.h | 40 +- llvm/lib/Transforms/Coroutines/CoroInternal.h | 4 +- llvm/lib/Transforms/Coroutines/CoroSplit.cpp | 100 +- llvm/lib/Transforms/Coroutines/Coroutines.cpp | 25 +- llvm/lib/Transforms/Scalar/LoopPredication.cpp | 2 +- llvm/lib/Transforms/Scalar/NewGVN.cpp | 12 - llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 3 +- .../Analysis/BlockFrequencyInfo/redundant_edges.ll | 2 +- llvm/test/Analysis/BranchProbabilityInfo/basic.ll | 40 +- .../BranchProbabilityInfo/deopt-intrinsic.ll | 4 +- .../Analysis/BranchProbabilityInfo/deopt-invoke.ll | 107 ++ llvm/test/Analysis/BranchProbabilityInfo/loop.ll | 209 ++- .../Analysis/BranchProbabilityInfo/noreturn.ll | 35 +- .../Analysis/BranchProbabilityInfo/unreachable.ll | 154 ++ .../irtranslator-invoke-probabilities.ll | 2 +- .../GlobalISel/extractelement-stack-lower.ll | 1675 +++++++++++--------- .../CodeGen/AMDGPU/GlobalISel/extractelement.ll | 16 +- .../test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll | 749 +++++++++ .../AMDGPU/GlobalISel/llvm.amdgcn.atomic.inc.ll | 260 ++- .../GlobalISel/llvm.amdgcn.global.atomic.fadd.ll | 30 +- .../CodeGen/AMDGPU/GlobalISel/load-constant.96.ll | 89 +- llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll | 11 +- .../CodeGen/AMDGPU/csr-sgpr-spill-live-ins.mir | 35 + llvm/test/CodeGen/AMDGPU/flat-scratch-fold-fi.mir | 88 + .../test/CodeGen/AMDGPU/frame-index-elimination.ll | 2 +- llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir | 16 + .../transform-block-with-return-to-epilog.ll | 4 +- llvm/test/CodeGen/AMDGPU/unaligned-load-store.ll | 69 +- llvm/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll | 2 +- llvm/test/CodeGen/ARM/sub-cmp-peephole.ll | 2 +- .../CodeGen/ARM/v8m.base-jumptable_alignment.ll | 22 +- llvm/test/CodeGen/PowerPC/p10-spill-crgt.ll | 182 +-- llvm/test/CodeGen/PowerPC/pr36292.ll | 5 +- llvm/test/CodeGen/PowerPC/sms-cpy-1.ll | 1 + llvm/test/CodeGen/RISCV/rvv/vfmacc-rv32.ll | 856 ++++++++++ llvm/test/CodeGen/RISCV/rvv/vfmacc-rv64.ll | 1142 +++++++++++++ llvm/test/CodeGen/RISCV/rvv/vfmadd-rv32.ll | 856 ++++++++++ llvm/test/CodeGen/RISCV/rvv/vfmadd-rv64.ll | 1142 +++++++++++++ llvm/test/CodeGen/RISCV/rvv/vfmax-rv32.ll | 881 ++++++++++ llvm/test/CodeGen/RISCV/rvv/vfmax-rv64.ll | 1201 ++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vfmerge-rv32.ll | 441 ++++++ llvm/test/CodeGen/RISCV/rvv/vfmerge-rv64.ll | 601 +++++++ llvm/test/CodeGen/RISCV/rvv/vfmin-rv32.ll | 881 ++++++++++ llvm/test/CodeGen/RISCV/rvv/vfmin-rv64.ll | 1201 ++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vfmsac-rv32.ll | 856 ++++++++++ llvm/test/CodeGen/RISCV/rvv/vfmsac-rv64.ll | 1142 +++++++++++++ llvm/test/CodeGen/RISCV/rvv/vfmsub-rv32.ll | 856 ++++++++++ llvm/test/CodeGen/RISCV/rvv/vfmsub-rv64.ll | 1142 +++++++++++++ llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv32.ll | 856 ++++++++++ llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv64.ll | 1142 +++++++++++++ llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv32.ll | 856 ++++++++++ llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv64.ll | 1142 +++++++++++++ llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv32.ll | 856 ++++++++++ llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv64.ll | 1142 +++++++++++++ llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv32.ll | 856 ++++++++++ llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv64.ll | 1142 +++++++++++++ llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv32.ll | 512 ++++++ llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv64.ll | 698 ++++++++ llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv32.ll | 523 ++++++ llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv64.ll | 713 +++++++++ llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv32.ll | 482 ++++++ llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv64.ll | 868 ++++++++++ llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv32.ll | 482 ++++++ llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv64.ll | 868 ++++++++++ llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv32.ll | 482 ++++++ llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv64.ll | 868 ++++++++++ llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv32.ll | 482 ++++++ llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv64.ll | 868 ++++++++++ llvm/test/CodeGen/RISCV/rvv/vmerge-rv32.ll | 973 ++++++++++++ llvm/test/CodeGen/RISCV/rvv/vmerge-rv64.ll | 1189 ++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vslide1down-rv32.ll | 800 ++++++++++ llvm/test/CodeGen/RISCV/rvv/vslide1down-rv64.ll | 978 ++++++++++++ llvm/test/CodeGen/RISCV/rvv/vslide1up-rv32.ll | 24 + llvm/test/CodeGen/RISCV/rvv/vslide1up-rv64.ll | 1000 ++++++++++++ llvm/test/CodeGen/RISCV/rvv/vwmacc-rv32.ll | 1034 ++++++++++++ llvm/test/CodeGen/RISCV/rvv/vwmacc-rv64.ll | 1412 +++++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv32.ll | 1034 ++++++++++++ llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv64.ll | 1412 +++++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv32.ll | 1034 ++++++++++++ llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv64.ll | 1412 +++++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv32.ll | 516 ++++++ llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv64.ll | 704 ++++++++ llvm/test/CodeGen/SPARC/missinglabel.ll | 2 +- llvm/test/CodeGen/SystemZ/debuginstr-cgp.mir | 4 +- llvm/test/CodeGen/Thumb2/schedm7-hazard.ll | 38 + llvm/test/CodeGen/VE/Vector/vec_and.ll | 132 ++ llvm/test/CodeGen/WebAssembly/simd-build-vector.ll | 6 +- llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll | 10 +- llvm/test/CodeGen/WebAssembly/simd-load-splat.ll | 2 +- .../WebAssembly/simd-load-store-alignment.ll | 36 +- .../CodeGen/WebAssembly/simd-nested-shuffles.ll | 2 +- llvm/test/CodeGen/WebAssembly/simd-offset.ll | 96 +- .../WebAssembly/simd-shift-complex-splats.ll | 2 +- .../CodeGen/WebAssembly/simd-shuffle-bitcast.ll | 2 +- llvm/test/CodeGen/WebAssembly/simd.ll | 48 +- .../WebAssembly/switch-unreachable-default.ll | 4 +- llvm/test/CodeGen/X86/2008-04-17-CoalescerBug.ll | 19 +- llvm/test/CodeGen/X86/block-placement.ll | 4 +- .../CodeGen/X86/misched_phys_reg_assign_order.ll | 6 +- llvm/test/CodeGen/X86/pr27501.ll | 10 +- llvm/test/CodeGen/X86/pr37916.ll | 2 +- llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll | 117 +- llvm/test/MC/Disassembler/WebAssembly/wasm.txt | 2 +- llvm/test/MC/WebAssembly/simd-encodings.s | 24 +- llvm/test/Object/elf-unknown-type.test | 10 - llvm/test/TableGen/substr.td | 81 + llvm/test/Transforms/Coroutines/coro-async.ll | 67 +- .../test/Transforms/JumpThreading/thread-prob-3.ll | 4 +- .../AMDGPU/adjust-alloca-alignment.ll | 35 +- llvm/test/Transforms/SLPVectorizer/X86/fmaxnum.ll | 147 ++ llvm/test/Transforms/SLPVectorizer/X86/fminnum.ll | 147 ++ llvm/test/tools/llvm-readobj/ELF/file-types.test | 10 +- llvm/tools/llvm-readobj/ELFDumper.cpp | 49 +- mlir/docs/ConversionToLLVMDialect.md | 467 ------ mlir/docs/LLVMDialectMemRefConvention.md | 439 +++++ mlir/examples/toy/Ch6/mlir/LowerToLLVM.cpp | 21 +- mlir/examples/toy/Ch7/mlir/LowerToLLVM.cpp | 21 +- .../StandardToLLVM/ConvertStandardToLLVM.h | 13 +- mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td | 32 +- mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.h | 182 +-- mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td | 9 +- mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td | 5 + .../Dialect/SPIRV/IR/SPIRVGLSLCanonicalization.h | 31 + mlir/include/mlir/IR/ImplicitLocOpBuilder.h | 123 ++ .../include/mlir/Target/LLVMIR/ModuleTranslation.h | 3 + mlir/lib/Conversion/AsyncToLLVM/AsyncToLLVM.cpp | 156 +- .../GPUCommon/ConvertLaunchFuncToRuntimeCalls.cpp | 105 +- mlir/lib/Conversion/GPUCommon/GPUOpsLowering.h | 24 +- .../GPUCommon/IndexIntrinsicsOpLowering.h | 13 +- .../Conversion/GPUCommon/OpToFuncCallLowering.h | 14 +- .../Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp | 8 +- .../GPUToVulkan/ConvertLaunchFuncToVulkanCalls.cpp | 106 +- mlir/lib/Conversion/LinalgToLLVM/LinalgToLLVM.cpp | 2 +- .../SPIRVToLLVM/ConvertLaunchFuncToLLVMCalls.cpp | 7 +- .../Conversion/SPIRVToLLVM/ConvertSPIRVToLLVM.cpp | 28 +- .../Conversion/StandardToLLVM/StandardToLLVM.cpp | 263 +-- .../StandardToSPIRV/ConvertStandardToSPIRV.cpp | 8 +- .../VectorToLLVM/ConvertVectorToLLVM.cpp | 48 +- .../lib/Conversion/VectorToROCDL/VectorToROCDL.cpp | 10 +- mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp | 248 +-- mlir/lib/Dialect/LLVMIR/IR/LLVMTypes.cpp | 283 +--- mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp | 22 +- mlir/lib/Dialect/LLVMIR/IR/ROCDLDialect.cpp | 12 +- mlir/lib/Dialect/SPIRV/IR/CMakeLists.txt | 1 + mlir/lib/Dialect/SPIRV/IR/SPIRVCanonicalization.td | 30 + .../Dialect/SPIRV/IR/SPIRVGLSLCanonicalization.cpp | 35 + .../Dialect/SPIRV/Transforms/SPIRVConversion.cpp | 12 +- mlir/lib/ExecutionEngine/JitRunner.cpp | 19 +- mlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp | 45 +- mlir/lib/Target/LLVMIR/ModuleTranslation.cpp | 136 +- .../lower-memcpy-to-gpu-runtime-calls.mlir | 19 + .../StandardToSPIRV/std-ops-to-spirv.mlir | 26 + mlir/test/Dialect/LLVMIR/invalid.mlir | 8 +- .../SPIRV/Transforms/glsl_canonicalize.mlir | 113 ++ mlir/test/Target/openmp-llvm.mlir | 34 +- mlir/test/lib/Dialect/SPIRV/CMakeLists.txt | 1 + .../lib/Dialect/SPIRV/TestGLSLCanonicalization.cpp | 39 + mlir/test/lib/Transforms/TestConvertCallOp.cpp | 3 +- .../mlir-cuda-runner/cuda-runtime-wrappers.cpp | 7 + mlir/tools/mlir-opt/mlir-opt.cpp | 2 + .../mlir-rocm-runner/rocm-runtime-wrappers.cpp | 5 + openmp/docs/SupportAndFAQ.rst | 31 +- openmp/docs/design/Runtimes.rst | 82 + 276 files changed, 52049 insertions(+), 4855 deletions(-) delete mode 100644 clang/test/SemaTemplate/instantiation-dependence.cpp create mode 100644 llvm/test/Analysis/BranchProbabilityInfo/deopt-invoke.ll create mode 100644 llvm/test/Analysis/BranchProbabilityInfo/unreachable.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll create mode 100644 llvm/test/CodeGen/AMDGPU/csr-sgpr-spill-live-ins.mir create mode 100644 llvm/test/CodeGen/AMDGPU/flat-scratch-fold-fi.mir create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmacc-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmacc-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmadd-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmadd-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmax-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmax-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmerge-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmerge-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmin-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmin-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmsac-rv32.ll create mode 100644 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