This is an automated email from the git hooks/post-receive script.
tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_bootstrap/master-aarch64-bootstrap in repository toolchain/ci/gcc.
from fe79d652c96 target/104581 - compile-time regression in mode-switching adds df5ed150ee5 rs6000: Fix up posix_memalign call in _mm_malloc [PR104598] new 1931cbad498 pieces-memset-21.c: Expect vzeroupper for ia32
The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.
Summary of changes: gcc/config/rs6000/mm_malloc.h | 2 +- gcc/testsuite/gcc.target/i386/pieces-memset-21.c | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-)