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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-next-allyesconfig in repository toolchain/ci/llvm-project.

from f59cc9542bfb Reland "[Clang] Extend -Wbool-operation to warn about bitw [...] adds 5aca8bb963a4 [clang-format] allow clang-format to be passed a file of f [...] adds a76355d570a9 Unbreak hexagon-check-builtins.c due to rGb1fcca388441 adds 31d0c8f35556 [X86] Add SSE2/AVX1/AVX512BW test coverage to interleaved [...] adds e311cdd18d21 [NFC][X86][LV] Add costmodel test coverage for interleaved [...] adds 9505fe29112c [NFC][X86][Codegen] Add test coverage for interleaved i8 l [...] adds 5f2f6118800f Fixed more warnings in LLVM produced by -Wbitwise-instead- [...] adds fb84aa2a8f52 Fixed warnings in target/parser codes produced by -Wbitwis [...] adds f3c6c76cfd0d [NFC][X86][LV] Add costmodel test coverage for interleaved [...] adds a834849aacad [NFC][X86][Codegen] Add test coverage for interleaved i32 [...] adds 3be4acbaa356 [InstSimplify] Add additional load from constant test (NFC) adds 88a9c1827e8d [InstCombine] add test for shl + demanded bits; NFC adds f32c0fe8e505 [InstCombine] fold cast of right-shift if high bits are no [...] adds 025ce154356f [NFC][X86][LV] Add costmodel test coverage for interleaved [...] adds 9afec8890743 [NFC][X86][Codegen] Add test coverage for interleaved i64 [...] adds d34cd75d890a [Analysis, CodeGen] Migrate from arg_operands to args (NFC) adds d6482df683b9 [ARM] Tests for constant hoisting -1 immediates adds b85bf520dcd9 [CostModel][X86] X86TTIImpl::getCmpSelInstrCost - try to u [...] adds 164cc2781fb1 [X86] Split Cannonlake + Icelake Tuning. NFC adds 20b1a16a696a [ARM] Mark <= -1 immediate constant as cheap adds 0f567f0e3ed8 [mlir] [test] Add missing tool substitutions

No new revisions were added by this update.

Summary of changes: clang/docs/tools/clang-formatted-files.txt | 7925 ++++++++++++++++++++ clang/docs/tools/generate_formatted_state.py | 23 +- clang/lib/Lex/PPExpressions.cpp | 4 +- clang/lib/Sema/SemaChecking.cpp | 4 +- clang/tools/clang-format/ClangFormat.cpp | 21 +- llvm/include/llvm/Transforms/IPO/Attributor.h | 2 +- llvm/lib/Analysis/AliasAnalysis.cpp | 2 +- llvm/lib/Analysis/BasicAliasAnalysis.cpp | 3 +- llvm/lib/Analysis/ConstantFolding.cpp | 4 +- llvm/lib/Analysis/InstructionSimplify.cpp | 4 +- llvm/lib/Analysis/LazyValueInfo.cpp | 4 +- llvm/lib/AsmParser/LLParser.cpp | 6 +- llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 5 +- llvm/lib/CodeGen/IntrinsicLowering.cpp | 3 +- llvm/lib/CodeGen/SelectionDAG/FastISel.cpp | 4 +- .../CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 16 +- .../CodeGen/SelectionDAG/StatepointLowering.cpp | 2 +- llvm/lib/CodeGen/TypePromotion.cpp | 6 +- llvm/lib/IR/Instruction.cpp | 10 +- .../Target/AMDGPU/AMDGPUInstructionSelector.cpp | 5 +- llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp | 8 + llvm/lib/Target/Lanai/LanaiAluCode.h | 2 +- llvm/lib/Target/Mips/MipsSubtarget.cpp | 2 +- llvm/lib/Target/X86/X86.td | 17 +- llvm/lib/Target/X86/X86TargetTransformInfo.cpp | 12 +- .../Transforms/InstCombine/InstCombineAddSub.cpp | 4 +- .../InstCombine/InstCombineSimplifyDemanded.cpp | 20 +- llvm/lib/Transforms/Utils/BuildLibCalls.cpp | 5 +- .../Transforms/Vectorize/LoadStoreVectorizer.cpp | 41 +- .../CostModel/X86/interleaved-load-f32-stride-3.ll | 75 + .../CostModel/X86/interleaved-load-f64-stride-3.ll | 75 + .../CostModel/X86/interleaved-load-i32-stride-3.ll | 75 + .../CostModel/X86/interleaved-load-i64-stride-3.ll | 75 + .../CostModel/X86/interleaved-load-i8-stride-6.ll | 88 + .../X86/interleaved-store-f32-stride-3.ll | 76 + .../X86/interleaved-store-f64-stride-3.ll | 76 + .../X86/interleaved-store-i32-stride-3.ll | 76 + .../X86/interleaved-store-i64-stride-3.ll | 76 + .../CostModel/X86/interleaved-store-i8-stride-6.ll | 89 + llvm/test/CodeGen/ARM/consthoist-icmpimm.ll | 823 ++ .../X86/vector-interleaved-load-i16-stride-2.ll | 373 +- .../X86/vector-interleaved-load-i16-stride-3.ll | 735 +- .../X86/vector-interleaved-load-i16-stride-4.ll | 993 ++- .../X86/vector-interleaved-load-i16-stride-5.ll | 819 +- .../X86/vector-interleaved-load-i16-stride-6.ll | 1072 ++- .../X86/vector-interleaved-load-i32-stride-2.ll | 309 +- .../X86/vector-interleaved-load-i32-stride-3.ll | 715 ++ .../X86/vector-interleaved-load-i64-stride-2.ll | 277 +- .../X86/vector-interleaved-load-i64-stride-3.ll | 653 ++ .../X86/vector-interleaved-load-i8-stride-2.ll | 250 +- .../X86/vector-interleaved-load-i8-stride-3.ll | 727 +- .../X86/vector-interleaved-load-i8-stride-4.ll | 903 ++- .../X86/vector-interleaved-load-i8-stride-6.ll | 2669 +++++++ .../X86/vector-interleaved-store-i16-stride-2.ll | 253 +- .../X86/vector-interleaved-store-i16-stride-3.ll | 611 +- .../X86/vector-interleaved-store-i16-stride-4.ll | 1043 ++- .../X86/vector-interleaved-store-i16-stride-5.ll | 707 +- .../X86/vector-interleaved-store-i16-stride-6.ll | 518 +- .../X86/vector-interleaved-store-i32-stride-2.ll | 329 +- .../X86/vector-interleaved-store-i32-stride-3.ll | 717 ++ .../X86/vector-interleaved-store-i64-stride-2.ll | 280 +- .../X86/vector-interleaved-store-i64-stride-3.ll | 654 ++ .../X86/vector-interleaved-store-i8-stride-2.ll | 187 +- .../X86/vector-interleaved-store-i8-stride-3.ll | 500 +- .../X86/vector-interleaved-store-i8-stride-4.ll | 393 +- .../X86/vector-interleaved-store-i8-stride-6.ll | 1527 ++++ llvm/test/Transforms/InstCombine/shl-demand.ll | 17 + llvm/test/Transforms/InstCombine/trunc-demand.ll | 56 +- .../Transforms/InstSimplify/ConstProp/loads.ll | 11 + mlir/test/lit.cfg.py | 3 + 70 files changed, 27127 insertions(+), 942 deletions(-) create mode 100644 clang/docs/tools/clang-formatted-files.txt create mode 100644 llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-3.ll create mode 100644 llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-3.ll create mode 100644 llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-3.ll create mode 100644 llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-3.ll create mode 100644 llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-6.ll create mode 100644 llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-3.ll create mode 100644 llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-3.ll create mode 100644 llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-3.ll create mode 100644 llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-3.ll create mode 100644 llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-6.ll create mode 100644 llvm/test/CodeGen/ARM/consthoist-icmpimm.ll create mode 100644 llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-3.ll create mode 100644 llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-3.ll create mode 100644 llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-6.ll create mode 100644 llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-3.ll create mode 100644 llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-3.ll create mode 100644 llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-6.ll