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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-mainline-allmodconfig in repository toolchain/ci/qemu.

from 3757b0d08b Merge tag 'pull-request-2022-05-18' of https://gitlab.com/th [...] new d6cd3ae0eb target/riscv: Fix VS mode hypervisor CSR access new 02b511985e target/riscv: rvv: Fix early exit condition for whole regist [...] new 77046729f9 hw/intc: Pass correct hartid while updating mtimecmp new 6047dcc245 target/riscv: Move Zhinx* extensions on ISA string new a4a9a4432e target/riscv: Add short-isa-string option new 4bcfc391ac hw/riscv: Make CPU config error handling generous (virt/spike) new 91a3387dc4 hw/riscv: Make CPU config error handling generous (sifive_e/ [...] new 61cdf4593e target/riscv: Fix coding style on "G" expansion new 1d398ab9dc target/riscv: Disable "G" by default new 9f6b7da5d2 target/riscv: Change "G" expansion new 1086504c6f target/riscv: FP extension requirements new bc57381669 target/riscv: Move/refactor ISA extension checks new 8f1b608798 hw/vfio/pci-quirks: Resolve redundant property getters new 96c7fff703 hw/riscv/sifive_u: Resolve redundant property accessors new bb06941f95 target/riscv: check 'I' and 'E' after checking 'G' in riscv_ [...] new 075eeda931 target/riscv: Fix typo of mimpid cpu option new c1fbcecb3a target/riscv: Fix csr number based privilege checking new 24826da0ee target/riscv: Fix hstatus.GVA bit setting for traps taken fr [...] new 62cf02451e target/riscv: Set [m|s]tval for both illegal and virtual ins [...] new d644e5e44f hw/riscv: virt: Fix interrupt parent for dynamic platform devices new 5160bacc06 target/riscv: add zicsr/zifencei to isa_string new d616889ece hw/core: Sync uboot_image.h from U-Boot v2022.01 new 8fe63fe8e5 hw/core: loader: Set is_linux to true for VxWorks uImage new 0cac736e73 Merge tag 'pull-riscv-to-apply-20220525' of github.com:alist [...]

The 24 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.

Summary of changes: hw/core/loader.c | 15 +++ hw/core/uboot_image.h | 213 +++++++++++++++++++++----------- hw/intc/riscv_aclint.c | 3 +- hw/riscv/opentitan.c | 2 +- hw/riscv/sifive_e.c | 2 +- hw/riscv/sifive_u.c | 28 +---- hw/riscv/spike.c | 2 +- hw/riscv/virt.c | 27 ++-- hw/vfio/pci-quirks.c | 34 ++--- target/riscv/cpu.c | 91 ++++++++++---- target/riscv/cpu.h | 12 +- target/riscv/cpu_helper.c | 4 +- target/riscv/csr.c | 26 ++-- target/riscv/insn_trans/trans_rvv.c.inc | 58 +++++---- target/riscv/translate.c | 17 ++- 15 files changed, 325 insertions(+), 209 deletions(-)