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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-defconfig in repository toolchain/binutils-gdb.

from 38139a9681 valops.c: Overload resolution code: Rename parameters/locals adds b5ffee3181 gdb/riscv: Add target description support adds ca94519e70 Fix linking MSP430 files created by gcc's LTO optimizer. adds 1c97054b87 Make command-repeat work after gdb.execute adds 51534d7ab8 S12Z: Add alias instructions BHS and BLO. adds 27f42a4ddb S12Z opcodes: Fix bug disassembling certain shift instructions. adds 79a9468c70 Automatic date update in version.in

No new revisions were added by this update.

Summary of changes: bfd/ChangeLog | 6 + bfd/elf32-msp430.c | 6 + bfd/version.h | 2 +- gas/ChangeLog | 11 + gas/config/tc-s12z.c | 2 + gas/testsuite/gas/s12z/bra.d | 6 +- gas/testsuite/gas/s12z/bra.s | 2 + gas/testsuite/gas/s12z/shift.d | 4 +- gas/testsuite/gas/s12z/shift.s | 2 + gdb/ChangeLog | 72 +++ gdb/Makefile.in | 2 + gdb/NEWS | 2 + gdb/arch/riscv.c | 69 +++ gdb/arch/riscv.h | 64 +++ gdb/configure.tgt | 9 +- gdb/doc/ChangeLog | 5 + gdb/doc/gdb.texinfo | 36 ++ gdb/features/Makefile | 11 + gdb/features/riscv/32bit-cpu.c | 46 ++ gdb/features/riscv/32bit-cpu.xml | 43 ++ gdb/features/riscv/32bit-csr.c | 253 ++++++++++ gdb/features/riscv/32bit-csr.xml | 250 ++++++++++ gdb/features/riscv/32bit-fpu.c | 48 ++ gdb/features/riscv/32bit-fpu.xml | 46 ++ gdb/features/riscv/64bit-cpu.c | 46 ++ gdb/features/riscv/64bit-cpu.xml | 43 ++ gdb/features/riscv/64bit-csr.c | 253 ++++++++++ gdb/features/riscv/64bit-csr.xml | 250 ++++++++++ gdb/features/riscv/64bit-fpu.c | 56 +++ gdb/features/riscv/64bit-fpu.xml | 52 ++ gdb/features/riscv/rebuild-csr-xml.sh | 29 ++ gdb/python/python.c | 3 +- gdb/riscv-tdep.c | 888 ++++++++++++++++++++-------------- gdb/riscv-tdep.h | 29 +- gdb/target-descriptions.c | 1 + gdb/testsuite/ChangeLog | 6 + gdb/testsuite/gdb.python/python.exp | 1 + opcodes/ChangeLog | 5 + opcodes/s12z-dis.c | 44 +- 39 files changed, 2302 insertions(+), 401 deletions(-) create mode 100644 gdb/arch/riscv.c create mode 100644 gdb/arch/riscv.h create mode 100644 gdb/features/riscv/32bit-cpu.c create mode 100644 gdb/features/riscv/32bit-cpu.xml create mode 100644 gdb/features/riscv/32bit-csr.c create mode 100644 gdb/features/riscv/32bit-csr.xml create mode 100644 gdb/features/riscv/32bit-fpu.c create mode 100644 gdb/features/riscv/32bit-fpu.xml create mode 100644 gdb/features/riscv/64bit-cpu.c create mode 100644 gdb/features/riscv/64bit-cpu.xml create mode 100644 gdb/features/riscv/64bit-csr.c create mode 100644 gdb/features/riscv/64bit-csr.xml create mode 100644 gdb/features/riscv/64bit-fpu.c create mode 100644 gdb/features/riscv/64bit-fpu.xml create mode 100755 gdb/features/riscv/rebuild-csr-xml.sh