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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-next-allnoconfig in repository toolchain/ci/llvm-project.

from 375a84bb75a [clang-format] SpacesInSquareBrackets should affect lambdas [...] adds f609c0a303e BranchFolding - IsBetterFallthrough - assert non-null point [...] adds 20692a0d3d3 SemaStmt - silence static analyzer getAs<> null dereference [...] adds 0e82722f9a1 Remove redundant !HasDependentValue check. NFCI. adds 22b68731956 TreeTransform - silence static analyzer getAs<> null derefe [...] adds f4cc3b3e10e SemaTemplate - silence static analyzer getAs<> null derefer [...] adds 83b81c1f6ee [Diagnostics] Highlight expr's source range for -Wbool-operation adds 43bbca92284 RewriteObjC - silence static analyzer getAs<> null derefere [...] adds 41c934acaf8 [SelectionDAG] Add tests for LKK algorithm adds 68f21b360b9 Try to fix sphinx indentation error adds 9ecacb0d54f [X86] lowerShuffleAsLanePermuteAndRepeatedMask - variable r [...] adds e2321bb4488 [SLP] avoid reduction transform on patterns that the backen [...] adds 8815be04ec1 [X86][AVX] Push sign extensions of comparison bool results [...] adds 2decdf42b95 [FastISel] Copy the inline assembly dialect to the INLINEAS [...] adds 69c65a86097 AMDGPU/GlobalISel: Fix RegBankSelect for sendmsg intrinsics adds a5b9c756745 GlobalISel: Partially implement lower for G_EXTRACT adds bcd6b1d2090 AMDGPU/GlobalISel: Lower G_ATOMIC_CMPXCHG_WITH_SUCCESS adds c0ec72d4f85 AMDGPU/GlobalISel: RegBankSelect DS GWS intrinsics adds 786a3953bac AMDGPU/GlobalISel: RegBankSelect mul24 intrinsics adds e59296a0519 AMDGPU/GlobalISel: Fall back on weird G_EXTRACT offsets new c209598268b [clang-format][docs] Fix the Google C++ and Chromium style [...]

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Summary of changes: clang/docs/ClangFormatStyleOptions.rst | 2 +- clang/docs/ReleaseNotes.rst | 8 +- clang/lib/Frontend/Rewrite/RewriteObjC.cpp | 15 +- clang/lib/Sema/SemaExpr.cpp | 1 + clang/lib/Sema/SemaStmt.cpp | 12 +- clang/lib/Sema/SemaTemplate.cpp | 8 +- clang/lib/Sema/TreeTransform.h | 8 +- llvm/include/llvm/Analysis/TargetTransformInfo.h | 10 + .../llvm/CodeGen/GlobalISel/LegalizerHelper.h | 1 + llvm/lib/Analysis/TargetTransformInfo.cpp | 53 + llvm/lib/CodeGen/BranchFolding.cpp | 2 + llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 35 + llvm/lib/CodeGen/SelectionDAG/FastISel.cpp | 1 + .../Target/AMDGPU/AMDGPUInstructionSelector.cpp | 7 +- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 17 +- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 48 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 86 +- llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 15 +- llvm/test/CodeGen/AArch64/srem-lkk.ll | 149 ++ llvm/test/CodeGen/AArch64/srem-vector-lkk.ll | 324 ++++ llvm/test/CodeGen/AArch64/urem-lkk.ll | 103 ++ llvm/test/CodeGen/AArch64/urem-vector-lkk.ll | 267 ++++ .../GlobalISel/artifact-combiner-extract.mir | 14 +- .../legalize-atomic-cmpxchg-with-success.mir | 107 ++ .../GlobalISel/legalize-extract-vector-elt.mir | 20 +- .../CodeGen/AMDGPU/GlobalISel/legalize-extract.mir | 183 ++- .../AMDGPU/GlobalISel/legalize-shuffle-vector.mir | 20 +- .../regbankselect-amdgcn.ds.gws.init.mir | 79 + .../regbankselect-amdgcn.ds.gws.sema.v.mir | 37 + .../GlobalISel/regbankselect-amdgcn.s.sendmsg.mir | 13 +- .../regbankselect-amdgcn.s.sendmsghalt.mir | 15 +- .../AMDGPU/GlobalISel/regbankselect-constant.mir | 8 +- llvm/test/CodeGen/PowerPC/srem-lkk.ll | 149 ++ llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll | 1675 +++++++++++++++++++ llvm/test/CodeGen/PowerPC/urem-lkk.ll | 106 ++ llvm/test/CodeGen/PowerPC/urem-vector-lkk.ll | 1338 ++++++++++++++++ llvm/test/CodeGen/RISCV/srem-lkk.ll | 583 +++++++ llvm/test/CodeGen/RISCV/srem-vector-lkk.ll | 1689 ++++++++++++++++++++ llvm/test/CodeGen/RISCV/urem-lkk.ll | 354 ++++ llvm/test/CodeGen/RISCV/urem-vector-lkk.ll | 1419 ++++++++++++++++ llvm/test/CodeGen/X86/bitcast-and-setcc-256.ll | 161 +- llvm/test/CodeGen/X86/bitcast-and-setcc-512.ll | 124 +- llvm/test/CodeGen/X86/pr43575.ll | 14 + llvm/test/CodeGen/X86/srem-lkk.ll | 159 ++ llvm/test/CodeGen/X86/srem-vector-lkk.ll | 556 +++++++ llvm/test/CodeGen/X86/urem-lkk.ll | 108 ++ llvm/test/CodeGen/X86/urem-vector-lkk.ll | 378 +++++ .../Transforms/SLPVectorizer/X86/bad-reduction.ll | 156 +- 48 files changed, 10312 insertions(+), 325 deletions(-) create mode 100644 llvm/test/CodeGen/AArch64/srem-lkk.ll create mode 100644 llvm/test/CodeGen/AArch64/srem-vector-lkk.ll create mode 100644 llvm/test/CodeGen/AArch64/urem-lkk.ll create mode 100644 llvm/test/CodeGen/AArch64/urem-vector-lkk.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomic-cmpxchg-wit [...] create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws [...] create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws [...] create mode 100644 llvm/test/CodeGen/PowerPC/srem-lkk.ll create mode 100644 llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll create mode 100644 llvm/test/CodeGen/PowerPC/urem-lkk.ll create mode 100644 llvm/test/CodeGen/PowerPC/urem-vector-lkk.ll create mode 100644 llvm/test/CodeGen/RISCV/srem-lkk.ll create mode 100644 llvm/test/CodeGen/RISCV/srem-vector-lkk.ll create mode 100644 llvm/test/CodeGen/RISCV/urem-lkk.ll create mode 100644 llvm/test/CodeGen/RISCV/urem-vector-lkk.ll create mode 100644 llvm/test/CodeGen/X86/pr43575.ll create mode 100644 llvm/test/CodeGen/X86/srem-lkk.ll create mode 100644 llvm/test/CodeGen/X86/srem-vector-lkk.ll create mode 100644 llvm/test/CodeGen/X86/urem-lkk.ll create mode 100644 llvm/test/CodeGen/X86/urem-vector-lkk.ll