This is an automated email from the git hooks/post-receive script.

tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_llvm_tx1/llvm-master-aarch64-spec2k6-O2 in repository toolchain/ci/llvm-project.

from f04e387055e4 Making the code compliant to the documentation about Float [...] adds 9534e361ea12 [fir] Add placeholder conversion pattern for disptach operations adds 39f4ef81463d [fir] Add fir.select_case conversion adds b67be520548e [fir] Add !fir.field type conversion adds b241226aec1b [mlir][linalg] Avoid illegal elementwise fusion into reductions adds ce227ce3b38d [CodeGen] Use MachineInstr::operands (NFC) adds 9ba73b60995b [AMDGPU] Fix line endings adds 417add4d4e92 [CodeGen] Tweak whitespace in LiveInterval printing adds 8313b47a5807 [AMDGPU] Regenerate some div/rem test checks adds 11522cfcad6b [DAGCombiner] add fold for vselect based on mask of signbi [...] adds 72362736c380 [AIX] Set D111860's test unsupported on AIX adds 18fe0a0d9eb1 [PowerPC] PPC backend optimization to lower int_ppc_tdw/in [...] adds 4d8db4a9970e [libc++] Fix GDB pretty printer test on 32 bit targets adds f0d5a60fc1a4 [libc++] Implement P1147R1 (Printing volatile T*) adds ee7a006ce461 [RISCV] Promote f16 ceil/floor/round/roundeven/nearbyint/r [...] adds 816d184d44d2 Split headers from implementations in MLIR C API Bazel build. adds 8e85717dbf2f [RISCV] Fix non-sensical intrinsic names in rv64i-single-s [...]

No new revisions were added by this update.

Summary of changes: .../test/Modules/merge-objc-protocol-visibility.m | 1 + flang/include/flang/Optimizer/Dialect/FIROps.td | 2 + flang/lib/Optimizer/CodeGen/CodeGen.cpp | 171 +- flang/lib/Optimizer/CodeGen/TypeConverter.h | 4 + flang/lib/Optimizer/Dialect/FIROps.cpp | 20 + flang/test/Fir/convert-to-llvm-invalid.fir | 42 + flang/test/Fir/convert-to-llvm.fir | 152 + flang/test/Fir/types-to-llvm.fir | 8 + libcxx/docs/Status/Cxx2bPapers.csv | 2 +- libcxx/include/ostream | 9 + .../test/libcxx/gdb/gdb_pretty_printer_test.sh.cpp | 8 +- .../pointer.volatile.pass.cpp | 77 + llvm/lib/CodeGen/LiveInterval.cpp | 8 +- llvm/lib/CodeGen/LiveIntervals.cpp | 15 +- llvm/lib/CodeGen/LiveRangeEdit.cpp | 19 +- llvm/lib/CodeGen/MachineBasicBlock.cpp | 20 +- llvm/lib/CodeGen/ModuloSchedule.cpp | 10 +- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 21 + llvm/lib/CodeGen/VirtRegMap.cpp | 6 +- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 44 + llvm/lib/Target/PowerPC/PPCInstr64Bit.td | 2 - llvm/lib/Target/PowerPC/PPCInstrInfo.td | 2 - llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 9 +- llvm/test/CodeGen/AArch64/vselect-constants.ll | 20 +- .../CodeGen/AMDGPU/GlobalISel/legalize-sdiv.mir | 5780 ++++++++++---------- .../CodeGen/AMDGPU/GlobalISel/legalize-srem.mir | 5498 +++++++++---------- .../CodeGen/AMDGPU/GlobalISel/legalize-udiv.mir | 4822 ++++++++-------- .../CodeGen/AMDGPU/GlobalISel/legalize-urem.mir | 4600 ++++++++-------- llvm/test/CodeGen/AMDGPU/carryout-selection.ll | 796 +-- .../builtins-ppc-xlcompat-trap-64bit-only.ll | 207 + .../CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll | 207 + llvm/test/CodeGen/RISCV/half-intrinsics.ll | 350 ++ llvm/test/CodeGen/RISCV/rv64i-single-softfloat.ll | 59 +- llvm/test/CodeGen/X86/vselect-zero.ll | 144 +- .../Linalg/Transforms/ElementwiseOpFusion.cpp | 93 +- .../Dialect/Linalg/fusion-elementwise-ops.mlir | 38 + utils/bazel/llvm-project-overlay/mlir/BUILD.bazel | 174 +- .../bazel/llvm-project-overlay/mlir/build_defs.bzl | 37 + 38 files changed, 12468 insertions(+), 11009 deletions(-) create mode 100644 libcxx/test/std/input.output/iostream.format/output.streams/ost [...]