This is an automated email from the git hooks/post-receive script.

tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_bootstrap/master-aarch64-bootstrap_ubsan in repository toolchain/ci/binutils-gdb.

from 1ee4d0e313 sim: frv: flip trapdump default back to off adds 7cfa8d93cb [gdb/testsuite] Add gdb.opt/break-on-_exit.exp adds b08625af20 gdb: adjust x_file fields on COFF readers adds 14f458590a arm: enable Cortex-A710 CPU adds 0c7af29227 Handle PIE in .debug_loclists adds 2ec453b566 Automatic date update in version.in adds 23ec4a527d sim: synacor: simplify test generation adds bebe33486c sim: testsuite: delete unused arm remote host logic adds 40f6466678 sim: io: tweak compiler workaround with error output adds f0f2906ca0 sim: cris: stop testing a.out explicitly [ld/13900] adds efe113047d sim: testsuite: drop sim_compile cover function adds f786c359c1 RISC-V: Dump objects according to the elf architecture attribute. adds 585d6e39eb [gdb/testsuite] Add gdb.arch/ppc64-break-on-_exit.exp adds b038b53f1f [gdb/build] Fix build with -std=c++11 adds fdf95218bc [gdb/build] Fix Wimplicit-exception-spec-mismatch in clang build

No new revisions were added by this update.

Summary of changes: bfd/cpu-arm.c | 1 + bfd/elfnn-riscv.c | 27 ++--- bfd/elfxx-riscv.c | 69 ++++++++++++- bfd/elfxx-riscv.h | 8 +- bfd/version.h | 2 +- gas/NEWS | 2 + gas/config/tc-arm.c | 5 + gas/config/tc-riscv.c | 110 +++++--------------- gas/doc/c-arm.texi | 1 + gas/testsuite/gas/arm/cpu-cortex-a710.d | 6 ++ gas/testsuite/gas/riscv/mapping-04b.d | 4 +- gas/testsuite/gas/riscv/mapping-norelax-03b.d | 2 +- gas/testsuite/gas/riscv/mapping-norelax-04b.d | 4 +- gdb/coffread.c | 8 +- gdb/dwarf2/loc.c | 31 +++--- gdb/testsuite/gdb.arch/ppc64-break-on-_exit-main.c | 27 +++++ gdb/testsuite/gdb.arch/ppc64-break-on-_exit.c | 112 +++++++++++++++++++++ gdb/testsuite/gdb.arch/ppc64-break-on-_exit.exp | 56 +++++++++++ gdb/testsuite/gdb.arch/ppc64-break-on-_exit.s | 108 ++++++++++++++++++++ gdb/testsuite/gdb.opt/break-on-_exit.c | 26 +++++ gdb/testsuite/gdb.opt/break-on-_exit.exp | 66 ++++++++++++ gdb/xcoffread.c | 6 +- gdbsupport/new-op.cc | 9 +- opcodes/riscv-dis.c | 32 ++++-- sim/common/sim-io.c | 6 +- sim/testsuite/arm/allinsn.exp | 8 -- sim/testsuite/arm/iwmmxt/iwmmxt.exp | 8 -- sim/testsuite/arm/xscale/xscale.exp | 8 -- sim/testsuite/cris/c/c.exp | 2 +- sim/testsuite/cris/c/helloaout.c | 14 --- sim/testsuite/example-synacor/allinsn.exp | 4 + sim/testsuite/lib/sim-defs.exp | 20 ---- 32 files changed, 581 insertions(+), 211 deletions(-) create mode 100644 gas/testsuite/gas/arm/cpu-cortex-a710.d create mode 100644 gdb/testsuite/gdb.arch/ppc64-break-on-_exit-main.c create mode 100644 gdb/testsuite/gdb.arch/ppc64-break-on-_exit.c create mode 100644 gdb/testsuite/gdb.arch/ppc64-break-on-_exit.exp create mode 100644 gdb/testsuite/gdb.arch/ppc64-break-on-_exit.s create mode 100644 gdb/testsuite/gdb.opt/break-on-_exit.c create mode 100644 gdb/testsuite/gdb.opt/break-on-_exit.exp delete mode 100644 sim/testsuite/cris/c/helloaout.c