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from 4a02f3a1f96 Fix compilation failure on FreeBSD new 37a6fbe6522 RISC-V: Add intrinsics support for SiFive Xsfvcp extensions. new cc8b8c0b692 RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensions. new 83bb288faa3 AArch64: Fold LD1/ST1 with ptrue to LDR/STR for 128-bit VLS

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Summary of changes: gcc/config/aarch64/aarch64.cc | 29 +- gcc/config/riscv/constraints.md | 10 + gcc/config/riscv/generic-vector-ooo.md | 4 + gcc/config/riscv/genrvv-type-indexer.cc | 9 + gcc/config/riscv/riscv-c.cc | 3 +- gcc/config/riscv/riscv-vector-builtins-shapes.cc | 48 ++ gcc/config/riscv/riscv-vector-builtins-shapes.h | 2 + gcc/config/riscv/riscv-vector-builtins-types.def | 40 + gcc/config/riscv/riscv-vector-builtins.cc | 362 ++++++++- gcc/config/riscv/riscv-vector-builtins.def | 30 +- gcc/config/riscv/riscv-vector-builtins.h | 8 + gcc/config/riscv/riscv.md | 5 +- gcc/config/riscv/sifive-vector-builtins-bases.cc | 78 ++ gcc/config/riscv/sifive-vector-builtins-bases.h | 3 + .../riscv/sifive-vector-builtins-functions.def | 45 ++ gcc/config/riscv/sifive-vector.md | 871 +++++++++++++++++++++ gcc/config/riscv/vector-iterators.md | 49 ++ gcc/config/riscv/vector.md | 3 +- .../gcc.target/aarch64/sve/cond_arith_6.c | 3 +- .../aarch64/sve/ldst_ptrue_128_to_neon.c | 48 ++ .../gcc.target/aarch64/sve/pcs/return_4_128.c | 39 +- .../gcc.target/aarch64/sve/pcs/return_5_128.c | 39 +- .../gcc.target/aarch64/sve/pcs/struct_3_128.c | 56 +- .../gcc.target/riscv/rvv/xsfvector/sf_vc_f.c | 88 +++ .../gcc.target/riscv/rvv/xsfvector/sf_vc_i.c | 132 ++++ .../gcc.target/riscv/rvv/xsfvector/sf_vc_v.c | 107 +++ .../gcc.target/riscv/rvv/xsfvector/sf_vc_x.c | 138 ++++ 27 files changed, 2145 insertions(+), 104 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/ldst_ptrue_128_to_neon.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_f.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_i.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_v.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_x.c