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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-stable-allyesconfig in repository toolchain/ci/llvm-project.

from ec13fed5867f [X86] lowerV8I16Shuffle - use explicit SmallVector<SDValue [...] adds d4e3c50b2bda [libc++] Define `namespace views` in its own detail header. adds 8475349bd639 [AARCH64] ssbs should be enabled by default for cortex-x1, [...] adds 6697c5bc3a1e [compiler-rt] [scudo] Use -mcrc32 on x86 when available adds c62053979489 [AArch64] Fix the upper limit for folded address offsets for COFF new 5c9eed741dbd [libc++] Make __dir_stream visibility declaration consistent new 87599bdabbd1 [RISCV] Store/restore RISCVMachineFunctionInfo into MIR YAML file new b6e91d4a331e [RISCV] Pre-commit for fixing stack offset for RVV object new d0f27fb44952 [RISCV] Fixing stack offset for RVV object with vararg in stack. new 2c4d288eae8b [RISCV][NFC] Add missing lit.local.cfg in test/CodeGen/MIR/RISCV/ new fe8a27acd716 [LV] Handle zero cost loops in selectInterleaveCount.

The 6 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.

Summary of changes: clang/test/Driver/aarch64-ssbs.c | 4 + clang/test/Preprocessor/aarch64-target-features.c | 2 +- compiler-rt/cmake/config-ix.cmake | 1 + compiler-rt/lib/scudo/CMakeLists.txt | 7 +- compiler-rt/lib/scudo/scudo_allocator.cpp | 4 +- compiler-rt/lib/scudo/scudo_crc32.cpp | 4 +- compiler-rt/lib/scudo/scudo_crc32.h | 12 +- compiler-rt/lib/scudo/standalone/CMakeLists.txt | 7 +- compiler-rt/lib/scudo/standalone/checksum.h | 8 +- compiler-rt/lib/scudo/standalone/chunk.h | 4 +- compiler-rt/lib/scudo/standalone/crc32_hw.cpp | 4 +- libcxx/include/CMakeLists.txt | 1 + libcxx/include/__filesystem/directory_entry.h | 2 +- libcxx/include/__ranges/views.h | 35 ++++ libcxx/include/module.modulemap | 1 + libcxx/include/ranges | 11 +- .../detail.headers/ranges/views.module.verify.cpp | 15 ++ llvm/lib/Support/AArch64TargetParser.cpp | 2 + llvm/lib/Target/AArch64/AArch64.td | 7 +- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 7 +- .../AArch64/GISel/AArch64PreLegalizerCombiner.cpp | 7 +- llvm/lib/Target/RISCV/CMakeLists.txt | 1 + llvm/lib/Target/RISCV/RISCVFrameLowering.cpp | 23 ++- llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.cpp | 30 +++ llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h | 25 +++ llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 23 +++ llvm/lib/Target/RISCV/RISCVTargetMachine.h | 8 + llvm/lib/Transforms/Vectorize/LoopVectorize.cpp | 22 ++- llvm/test/CodeGen/AArch64/fold-global-offsets.ll | 16 +- .../CostModel => CodeGen/MIR}/RISCV/lit.local.cfg | 0 .../CodeGen/MIR/RISCV/machine-function-info.mir | 138 +++++++++++++ .../rvv/wrong-stack-offset-for-rvv-object.mir | 220 +++++++++++++++++++++ ...-select-interleave-count-loop-with-cost-zero.ll | 50 +++++ 33 files changed, 640 insertions(+), 61 deletions(-) create mode 100644 libcxx/include/__ranges/views.h create mode 100644 libcxx/test/libcxx/diagnostics/detail.headers/ranges/views.modu [...] create mode 100644 llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.cpp copy llvm/test/{Analysis/CostModel => CodeGen/MIR}/RISCV/lit.local.cfg (100%) create mode 100644 llvm/test/CodeGen/MIR/RISCV/machine-function-info.mir create mode 100644 llvm/test/CodeGen/RISCV/rvv/wrong-stack-offset-for-rvv-object.mir create mode 100644 llvm/test/Transforms/LoopVectorize/X86/pr54413-select-interleav [...]