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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-next-allmodconfig in repository toolchain/ci/llvm-project.

from 60236fedc9b Revert "[msan] Check qsort input." and "[msan] Intercept qs [...] adds 6e8659c351f [libc++] Fix typo in std::midpoint adds 384a287a999 Remove a gcc 4.9 comparison as it doesn't make sense adds a0ce6155734 clang is now under the apache2 license adds 7ece0ee3dd7 features.html: Remove some old info adds d688a6739df AMDGPU/GlobalISel: Simplify code adds dff3f8d7424 AMDGPU/GlobalISel: Fix missing scc imp-def on scalar and/or/xor adds 42a26445f9e AMDGPU/GlobalISel: Fix misuse of div_scale intrinsics adds f9677c47573 Mips: Make test resistant to future changes adds 4af68667088 AMDGPU: Fix repeated word in comment adds df6879ec022 [lldb] Fix ARM32 inferior calls adds 4706a60e8a0 [lldb] [testsuite] Fix Linux fail: Unwind/thread-step-out-r [...] adds 1805d1f87d7 [lldb] Fix -Wstringop-truncation in PythonReadline.cpp adds 5a79cfa32d6 Customize simplified dumping and matching of LambdaExpr adds ce3ce9f4640 [lldb] Force the preprocessor to run in thread-step-out-ret [...] adds 75e500dd471 Add missing `REQUIRES: hexagon-registered-target` adds e192cc1f1bf [lldb] One more attempt to fix thread-step-out-ret-addr-che [...] adds 2947da9ff7d [lldb] disable thread-step-out-ret-addr-check on windows adds be1a9b3863b [Wdocumentation] Implement \anchor adds 70d592d68c7 [Analyzer] Use a reference in a range-based for adds d269255b951 [AArch64] Respect reserved registers while renaming in LdSt opt. adds 49b206f9580 [lldb][NFC] Remove all ASTContext getter wrappers from Clan [...] adds 19f9f374d9a [SimplifyLibCalls] require fast-math-flags for pow(X, -0.5) [...] adds 79c7fa31f3a [InstCombine] check alloc size in bitcast of geps fold (PR44321) adds 7cee2885867 Fix `-Wunused-variable` warning. NFC. adds d76202d3e35 Fix Wpedantic 'extra semicolon' warning. NFC. adds 6945d383b9e Fix "result of 32-bit shift implicitly converted to 64 bits [...] adds 189b7393d54 [lld][RISCV] Use an e_flags of 0 if there are only binary i [...] adds 452ca8e73f2 [NFC] test commit adds fc5102fb6e3 [NFC] test commit reverted adds 2203089a60d [analyzer] exploded-graph-rewriter: Fix string encodings in [...] adds bf03e17c570 [Lldb/Lua] Generate Lua Bindings

No new revisions were added by this update.

Summary of changes: clang/bindings/xml/comment-xml-schema.rng | 8 + clang/include/clang-c/Documentation.h | 7 +- clang/include/clang/AST/ASTNodeTraverser.h | 25 +- clang/include/clang/AST/Comment.h | 8 +- clang/include/clang/AST/CommentCommands.td | 13 +- clang/lib/AST/CommentSema.cpp | 1 + clang/lib/AST/JSONNodeDumper.cpp | 3 + clang/lib/AST/TextNodeDumper.cpp | 3 + clang/lib/ASTMatchers/ASTMatchFinder.cpp | 61 ++++- clang/lib/Index/CommentToXML.cpp | 8 + clang/lib/Sema/SemaDeclObjC.cpp | 2 +- .../Checkers/InnerPointerChecker.cpp | 6 +- .../StaticAnalyzer/Checkers/IteratorModeling.cpp | 22 +- .../StaticAnalyzer/Core/BugReporterVisitors.cpp | 2 +- clang/test/AST/ast-dump-comment.cpp | 5 + clang/test/Driver/hexagon-toolchain-elf.c | 1 + .../Inputs/CommentXML/valid-inline-command-01.xml | 9 + .../test/Index/comment-to-html-xml-conversion.cpp | 10 + clang/test/Index/comment-xml-schema.c | 2 + clang/test/Sema/warn-documentation.cpp | 7 + clang/tools/c-index-test/c-index-test.c | 3 + clang/tools/libclang/CXComment.cpp | 3 + clang/unittests/AST/ASTTraverserTest.cpp | 119 ++++++++ .../ASTMatchers/ASTMatchersTraversalTest.cpp | 28 ++ clang/utils/analyzer/exploded-graph-rewriter.py | 6 +- clang/www/features.html | 30 +- clang/www/index.html | 2 +- libcxx/include/numeric | 2 +- lld/ELF/Arch/RISCV.cpp | 5 +- lld/test/ELF/riscv-elf-flags.s | 8 + lldb/CMakeLists.txt | 4 +- lldb/include/lldb/Symbol/ClangASTContext.h | 16 -- lldb/scripts/CMakeLists.txt | 79 ++++-- lldb/scripts/lldb_lua.swig | 18 ++ lldb/source/API/CMakeLists.txt | 19 ++ lldb/source/Core/PluginManager.cpp | 2 +- lldb/source/Expression/IRExecutionUnit.cpp | 2 +- lldb/source/Expression/IRMemoryMap.cpp | 12 +- lldb/source/Host/common/HostInfoBase.cpp | 4 +- .../ExpressionParser/Clang/ClangASTSource.cpp | 6 +- .../ExpressionParser/Clang/ClangASTSource.h | 4 +- .../Clang/ClangExpressionParser.cpp | 2 +- .../Plugins/ExpressionParser/Clang/IRForTarget.cpp | 2 +- lldb/source/Plugins/Process/POSIX/CrashReason.cpp | 8 +- .../Plugins/ScriptInterpreter/Lua/CMakeLists.txt | 2 + lldb/source/Plugins/ScriptInterpreter/Lua/Lua.h | 5 + .../ScriptInterpreter/Python/PythonReadline.cpp | 2 +- lldb/source/Symbol/ClangASTContext.cpp | 147 ++++------ .../test/Shell/ScriptInterpreter/Lua/bindings.test | 6 + .../Unwind/Inputs/thread-step-out-ret-addr-check.s | 9 +- .../Unwind/thread-step-out-ret-addr-check.test | 5 +- .../Expression/ClangExpressionDeclMapTest.cpp | 2 +- lldb/unittests/ScriptInterpreter/Lua/LuaTests.cpp | 2 + .../TestingSupport/Symbol/ClangTestUtils.h | 2 +- llvm/include/llvm/IR/IntrinsicsAMDGPU.td | 2 +- llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp | 2 +- .../Target/AArch64/AArch64LoadStoreOptimizer.cpp | 5 +- .../Target/AMDGPU/AMDGPUInstructionSelector.cpp | 5 + llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 10 +- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 10 +- .../InstCombine/InstructionCombining.cpp | 10 +- llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp | 5 + .../stp-opt-with-renaming-reserved-regs.mir | 89 ++++++ .../CodeGen/AMDGPU/GlobalISel/inst-select-and.mir | 40 +-- .../CodeGen/AMDGPU/GlobalISel/inst-select-or.mir | 36 +-- .../CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir | 36 +-- .../CodeGen/AMDGPU/GlobalISel/legalize-fdiv.mir | 304 ++++++++++----------- .../CodeGen/Mips/branch-relaxation-with-hazard.ll | 2 + llvm/test/Transforms/InstCombine/gep-vector.ll | 36 ++- llvm/test/Transforms/InstCombine/pow-sqrt.ll | 36 ++- .../unittests/CodeGen/GlobalISel/LegalizerTest.cpp | 2 +- 71 files changed, 923 insertions(+), 476 deletions(-) create mode 100644 clang/test/Index/Inputs/CommentXML/valid-inline-command-01.xml create mode 100644 lld/test/ELF/riscv-elf-flags.s create mode 100644 lldb/scripts/lldb_lua.swig create mode 100644 lldb/test/Shell/ScriptInterpreter/Lua/bindings.test create mode 100644 llvm/test/CodeGen/AArch64/stp-opt-with-renaming-reserved-regs.mir