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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_build/master-arm in repository toolchain/ci/qemu.

from 213fda642d Merge tag 'pull-9p-20220616' of https://github.com/cschoeneb [...] adds 638b752da3 pci-bridge/cxl_upstream: Add a CXL switch upstream port adds 18cef1c6a5 pci-bridge/cxl_downstream: Add a CXL switch downstream port adds 3afcbb7b8e docs/cxl: Add switch documentation adds b595d6272e virtio/vhost-user: Fix wrong vhost notifier GPtrArray size adds 90519b9053 virtio-iommu: Add bypass mode support to assigned device adds 08f2030a2e virtio-iommu: Use recursive lock to avoid deadlock adds 23b5f0ff6d virtio-iommu: Add an assert check in translate routine adds 0e660a6f90 crypto: Introduce RSA algorithm adds 9ce305c8be vhost: also check queue state in the vhost_dev_set_log error [...] adds 8c97e4deec acpi/erst: fix fallthrough code upon validation failure adds a28498b1f9 Merge tag 'for_upstream' of git://git.kernel.org/pub/scm/vir [...]

No new revisions were added by this update.

Summary of changes: backends/cryptodev-builtin.c | 276 +++++++++++++++++++++++++++----- backends/cryptodev-vhost-user.c | 34 +++- backends/cryptodev.c | 32 ++-- docs/system/devices/cxl.rst | 88 ++++++++++- hw/acpi/erst.c | 3 + hw/cxl/cxl-host.c | 43 ++++- hw/pci-bridge/cxl_downstream.c | 249 +++++++++++++++++++++++++++++ hw/pci-bridge/cxl_upstream.c | 216 +++++++++++++++++++++++++ hw/pci-bridge/meson.build | 2 +- hw/virtio/trace-events | 1 + hw/virtio/vhost-user.c | 2 +- hw/virtio/vhost.c | 4 + hw/virtio/virtio-crypto.c | 323 ++++++++++++++++++++++++++++++-------- hw/virtio/virtio-iommu.c | 135 ++++++++++++++-- include/hw/cxl/cxl.h | 5 + include/hw/virtio/virtio-crypto.h | 5 +- include/hw/virtio/virtio-iommu.h | 4 +- include/sysemu/cryptodev.h | 83 ++++++++-- 18 files changed, 1345 insertions(+), 160 deletions(-) create mode 100644 hw/pci-bridge/cxl_downstream.c create mode 100644 hw/pci-bridge/cxl_upstream.c