Hi Will, Ben, Russell, Thomas,
Please review second version of patch that fixes TLB asid issue in big endian
V7 image.
Changes from v1:
Note previous patch subject line was 'ARM: tlb:
__flush_tlb_mm need to use int asid var for BE correct operation'
Added 'unsigned int' cast into ASID macro itself rather
then use intermediate 'int' variable in __flush_tlb_mm function.
This is done per v1 patch discussion at
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-October/202583.h…
Tested with Linaro BE topic branch on Arndale board. Both LE and BE
images were tested.
Thanks,
Victor
Victor Kamensky (1):
ARM: tlb: ASID macro should give 32bit result for BE correct operation
arch/arm/include/asm/mmu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--
1.8.1.4
Apologies for the noise, I resent this series but neglected to place
the word "PATCH" in the subject lines of the patches thus the patches
got blocked by the list server. Here is another go at a resend.
---
The following patches bring both HugeTLB support and Transparent
HugePage (THP) support to ARM for 2 levels of paging (i.e. without
LPAE).
This code has been tested on an Arndale board (Exynos 5250), and
is based on 3.11-rc1, with the hugepage simplification patch:
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-July/184117.html
HugeTLB and THP support for LPAE has already been merged in 3.11-rc1.
Hugepages can give nice performance boosts to workloads that put
pressure on the TLBs. I've observed uplifts of ~5% to some tasks
just by enabling hugepages via the libhugetlbfs tools. Other
people have observed decent performance boosts when huge pages
are enabled:
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-February/148835.…
I would appreciate any discussion on these patches, as there are
people who have an interest in having huge page support in
non-LPAE kernels.
Steve Capper (2):
ARM: mm: HugeTLB support for non-LPAE systems.
ARM: mm: Transparent huge page support for non-LPAE systems.
arch/arm/Kconfig | 4 +-
arch/arm/include/asm/hugetlb-2level.h | 126 +++++++++++++++++++++++++
arch/arm/include/asm/hugetlb.h | 4 +
arch/arm/include/asm/pgtable-2level.h | 170 ++++++++++++++++++++++++++++++++++
arch/arm/include/asm/pgtable-3level.h | 6 ++
arch/arm/include/asm/pgtable.h | 7 +-
arch/arm/include/asm/tlb.h | 10 +-
arch/arm/kernel/head.S | 10 +-
arch/arm/mm/fault.c | 13 ---
arch/arm/mm/fsr-2level.c | 4 +-
arch/arm/mm/hugetlbpage.c | 2 +-
arch/arm/mm/mmu.c | 27 ++++++
12 files changed, 360 insertions(+), 23 deletions(-)
create mode 100644 arch/arm/include/asm/hugetlb-2level.h
--
1.8.1.4
Hello,
I'm resending this series again, to try and provoke some discussion on
them.
Cheers,
--
Steve
---
The following patches bring both HugeTLB support and Transparent
HugePage (THP) support to ARM for 2 levels of paging (i.e. without
LPAE).
This code has been tested on an Arndale board (Exynos 5250), and
is based on 3.11-rc1, with the hugepage simplification patch:
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-July/184117.html
HugeTLB and THP support for LPAE has already been merged in 3.11-rc1.
Hugepages can give nice performance boosts to workloads that put
pressure on the TLBs. I've observed uplifts of ~5% to some tasks
just by enabling hugepages via the libhugetlbfs tools. Other
people have observed decent performance boosts when huge pages
are enabled:
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-February/148835.…
I would appreciate any discussion on these patches, as there are
people who have an interest in having huge page support in
non-LPAE kernels.
Steve Capper (2):
ARM: mm: HugeTLB support for non-LPAE systems.
ARM: mm: Transparent huge page support for non-LPAE systems.
arch/arm/Kconfig | 4 +-
arch/arm/include/asm/hugetlb-2level.h | 126 +++++++++++++++++++++++++
arch/arm/include/asm/hugetlb.h | 4 +
arch/arm/include/asm/pgtable-2level.h | 170 ++++++++++++++++++++++++++++++++++
arch/arm/include/asm/pgtable-3level.h | 6 ++
arch/arm/include/asm/pgtable.h | 7 +-
arch/arm/include/asm/tlb.h | 10 +-
arch/arm/kernel/head.S | 10 +-
arch/arm/mm/fault.c | 13 ---
arch/arm/mm/fsr-2level.c | 4 +-
arch/arm/mm/hugetlbpage.c | 2 +-
arch/arm/mm/mmu.c | 27 ++++++
12 files changed, 360 insertions(+), 23 deletions(-)
create mode 100644 arch/arm/include/asm/hugetlb-2level.h
--
1.8.1.4
From: Mark Brown <broonie(a)linaro.org>
Within a DAPM sequence we normally don't care about when exactly a register
write has completed so long as they happen in the order we requested. This
means that we can issue most of the writes we do asynchronously which
should maximise the ability of the underlying frameworks to keep the
hardware busy, providing a small performance improvement on some systems.
We currently ensure that all writes are completed both when changing to a
different device and when calling into the regulator and clock frameworks.
This should ensure that the previous ordering is maintained.
We also ensure that writes are completed prior to calling into widget
event functions since some event functions implement delays. This
should be improved in future so that widgets can disable this sync in
order to add extra writes.
Signed-off-by: Mark Brown <broonie(a)linaro.org>
xvdfvsd
---
sound/soc/soc-dapm.c | 24 ++++++++++++++++++++++--
1 file changed, 22 insertions(+), 2 deletions(-)
diff --git a/sound/soc/soc-dapm.c b/sound/soc/soc-dapm.c
index 25b9554..905e4c5 100644
--- a/sound/soc/soc-dapm.c
+++ b/sound/soc/soc-dapm.c
@@ -409,6 +409,12 @@ static inline void soc_widget_unlock(struct snd_soc_dapm_widget *w)
mutex_unlock(&w->platform->mutex);
}
+static void soc_dapm_async_complete(struct snd_soc_dapm_context *dapm)
+{
+ if (dapm->codec && dapm->codec->using_regmap)
+ regmap_async_complete(dapm->codec->control_data);
+}
+
static int soc_widget_update_bits_locked(struct snd_soc_dapm_widget *w,
unsigned short reg, unsigned int mask, unsigned int value)
{
@@ -417,8 +423,9 @@ static int soc_widget_update_bits_locked(struct snd_soc_dapm_widget *w,
int ret;
if (w->codec && w->codec->using_regmap) {
- ret = regmap_update_bits_check(w->codec->control_data,
- reg, mask, value, &change);
+ ret = regmap_update_bits_check_async(w->codec->control_data,
+ reg, mask, value,
+ &change);
if (ret != 0)
return ret;
} else {
@@ -1201,6 +1208,8 @@ int dapm_regulator_event(struct snd_soc_dapm_widget *w,
{
int ret;
+ soc_dapm_async_complete(w->dapm);
+
if (SND_SOC_DAPM_EVENT_ON(event)) {
if (w->on_val & SND_SOC_DAPM_REGULATOR_BYPASS) {
ret = regulator_allow_bypass(w->regulator, false);
@@ -1234,6 +1243,8 @@ int dapm_clock_event(struct snd_soc_dapm_widget *w,
if (!w->clk)
return -EIO;
+ soc_dapm_async_complete(w->dapm);
+
#ifdef CONFIG_HAVE_CLK
if (SND_SOC_DAPM_EVENT_ON(event)) {
return clk_prepare_enable(w->clk);
@@ -1426,6 +1437,7 @@ static void dapm_seq_check_event(struct snd_soc_card *card,
if (w->event && (w->event_flags & event)) {
pop_dbg(w->dapm->dev, card->pop_time, "pop test : %s %s\n",
w->name, ev_name);
+ soc_dapm_async_complete(w->dapm);
trace_snd_soc_dapm_widget_event_start(w, event);
ret = w->event(w, NULL, event);
trace_snd_soc_dapm_widget_event_done(w, event);
@@ -1498,6 +1510,7 @@ static void dapm_seq_run(struct snd_soc_card *card,
struct list_head *list, int event, bool power_up)
{
struct snd_soc_dapm_widget *w, *n;
+ struct snd_soc_dapm_context *d;
LIST_HEAD(pending);
int cur_sort = -1;
int cur_subseq = -1;
@@ -1528,6 +1541,9 @@ static void dapm_seq_run(struct snd_soc_card *card,
cur_subseq);
}
+ if (cur_dapm && w->dapm != cur_dapm)
+ soc_dapm_async_complete(cur_dapm);
+
INIT_LIST_HEAD(&pending);
cur_sort = -1;
cur_subseq = INT_MIN;
@@ -1586,6 +1602,10 @@ static void dapm_seq_run(struct snd_soc_card *card,
cur_dapm->seq_notifier(cur_dapm,
i, cur_subseq);
}
+
+ list_for_each_entry(d, &card->dapm_list, list) {
+ soc_dapm_async_complete(d);
+ }
}
static void dapm_widget_update(struct snd_soc_card *card)
--
1.8.4.rc3