On Mon, Oct 07, 2013 at 09:37:19PM -0700, Victor Kamensky wrote:
> In big endian mode mcpm_entry_point is first function
> that called on secondaries CPU. First it should switch
> CPU into big endian code.
>
> Signed-off-by: Victor Kamensky <victor.kamensky(a)linaro.org>
Providing Nico's also OK with it, I don't see a problem with this.
Minor cosmetic nit: please line up the ) after be with the others.
Not the end of the world, though.
Reviewed-by: Dave Martin <Dave.Martin(a)arm.com>
Cheers
---Dave
> ---
> arch/arm/common/mcpm_head.S | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm/common/mcpm_head.S b/arch/arm/common/mcpm_head.S
> index 39c96df..4f88f5e 100644
> --- a/arch/arm/common/mcpm_head.S
> +++ b/arch/arm/common/mcpm_head.S
> @@ -15,6 +15,7 @@
>
> #include <linux/linkage.h>
> #include <asm/mcpm.h>
> +#include <asm/assembler.h>
>
> #include "vlock.h"
>
> @@ -47,6 +48,7 @@
>
> ENTRY(mcpm_entry_point)
>
> + ARM_BE8(setend be)
> THUMB( adr r12, BSYM(1f) )
> THUMB( bx r12 )
> THUMB( .thumb )
> --
> 1.8.1.4
>
>
> _______________________________________________
> linaro-kernel mailing list
> linaro-kernel(a)lists.linaro.org
> http://lists.linaro.org/mailman/listinfo/linaro-kernel
From: Mark Brown <broonie(a)linaro.org>
Since it is quite common for single register raw or async writes to be
generated by rbtree cache syncs or firmware downloads and essentially all
hardware will be faster with only a single transfer optimise this case by
copying single values into the internal scratch buffer before sending.
Signed-off-by: Mark Brown <broonie(a)linaro.org>
---
drivers/base/regmap/regmap.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/base/regmap/regmap.c b/drivers/base/regmap/regmap.c
index 5754513..4866ae5 100644
--- a/drivers/base/regmap/regmap.c
+++ b/drivers/base/regmap/regmap.c
@@ -1118,6 +1118,16 @@ int _regmap_raw_write(struct regmap *map, unsigned int reg,
u8[0] |= map->write_flag_mask;
+ /*
+ * Essentially all I/O mechanisms will be faster with a single
+ * buffer to write. Since register syncs often generate raw
+ * writes of single registers optimise that case.
+ */
+ if (val != work_val && val_len == map->format.val_bytes) {
+ memcpy(work_val, val, map->format.val_bytes);
+ val = work_val;
+ }
+
if (async && map->bus->async_write) {
struct regmap_async *async;
--
1.8.4.rc3
On ARM the debug info is not present in the .eh_frame sections but
in .debug_frame instead, in dwarf format.
This patch set uses libunwind to load and parse the dwarf debug info from
the .debug_frame section if no .eh_frame_hdr section is found; also it
sets the hooks in the perf_regs and libunwind code for ARMv7.
Dependencies:
. if present, libunwind >= 1.1 is needed to prevent a segfault when
parsing the dwarf info,
. libunwind needs to be configured with --enable-debug-frame. Note:
--enable-debug-frame is automatically selected on ARM.
The generated perf binary has been tested on ARMv7 (OMAP4, Marvell
Armada XP) and x86_64, using the following commands:
perf record -g [dwarf] -- <binary>
perf report --sort symbol --call-graph --stdio
Jean Pihet (2):
perf tools: Check libunwind for availability of dwarf parsing feature
perf: parse the .debug_frame section in case .eh_frame is not present
Will Deacon (2):
ARM: perf: add support for perf registers API
ARM: perf: wire up perf_regs and unwind support for ARM
arch/arm/Kconfig | 2 +
arch/arm/include/uapi/asm/Kbuild | 1 +
arch/arm/include/uapi/asm/perf_regs.h | 23 ++++++++++
arch/arm/kernel/Makefile | 1 +
arch/arm/kernel/perf_regs.c | 30 +++++++++++++
tools/perf/arch/arm/Makefile | 3 ++
tools/perf/arch/arm/include/perf_regs.h | 54 ++++++++++++++++++++++++
tools/perf/arch/arm/util/unwind.c | 48 +++++++++++++++++++++
tools/perf/config/Makefile | 13 ++++--
tools/perf/config/feature-tests.mak | 21 ++++++++-
tools/perf/util/unwind.c | 75 ++++++++++++++++++++++++++-------
11 files changed, 251 insertions(+), 20 deletions(-)
create mode 100644 arch/arm/include/uapi/asm/perf_regs.h
create mode 100644 arch/arm/kernel/perf_regs.c
create mode 100644 tools/perf/arch/arm/include/perf_regs.h
create mode 100644 tools/perf/arch/arm/util/unwind.c
--
1.7.11.7
The CCI PMU is not a CPU PMU. As such the CCI PMU events can be
initiate from any proocessor. Set the valid_cpus mask to indicate
this.
Signed-off-by: Punit Agrawal <punit.agrawal(a)arm.com>
---
(using the correct list-address. Please ignore the previous mail if you
get a duplicate)
Hi Tixy,
Please pick this patch - it is required for the Linaro kernels to be
able to use CCI PMU.
The patch is based on top of your integration-linux-vexpress branch.
Cheers,
Punit
drivers/bus/arm-cci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/bus/arm-cci.c b/drivers/bus/arm-cci.c
index 57b0bc6..7363c7e 100644
--- a/drivers/bus/arm-cci.c
+++ b/drivers/bus/arm-cci.c
@@ -545,6 +545,7 @@ static int cci_pmu_init(struct arm_pmu *cci_pmu, struct platform_device *pdev)
cci_pmu->plat_device = pdev;
cci_pmu->num_events = pmu_get_max_counters();
+ cpumask_setall(&cci_pmu->valid_cpus);
return armpmu_register(cci_pmu, -1);
}
--
1.7.10.4