Linaro-uefi April 2016

linaro-uefi@lists.linaro.org

26 participants
37 discussions

[PATCH 1/3] Platforms/ARM/Juno: Fix IO window translate offset in PCIe root complex

by Sudeep Holla

XPress-RICH3 PCIe driver initialises the root complex with the same source and target address for IO window which makes translate offset 0. This patch fixes the translate offset for the IO window in Juno PCIe root complex ACPI table. Contributed-under: TianoCore Contribution Agreement 1.0 Cc: Ard Biesheuvel <ard.biesheuvel(a)linaro.org> Cc: Leif Lindholm <leif.lindholm(a)linaro.org> Signed-off-by: Sudeep Holla <sudeep.holla(a)arm.com> --- Platforms/ARM/Juno/AcpiTables/AcpiSsdtRootPci.asl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Platforms/ARM/Juno/AcpiTables/AcpiSsdtRootPci.asl b/Platforms/ARM/Juno/AcpiTables/AcpiSsdtRootPci.asl index 800d2cb3b2fb..ab5041db731a 100644 --- a/Platforms/ARM/Juno/AcpiTables/AcpiSsdtRootPci.asl +++ b/Platforms/ARM/Juno/AcpiTables/AcpiSsdtRootPci.asl @@ -109,7 +109,7 @@ DefinitionBlock("SsdtPci.aml", "SSDT", 1, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_OEM 0x00000000, // Granularity 0x5f800000, // Min Base Address 0x5fffffff, // Max Base Address - 0x5f800000, // Translate + 0x00000000, // Translate 0x00800000 // Length ) }) // Name(RBUF) -- 1.9.1

8 years, 1 month

[PATCH] Platforms/ARM: Juno: Acpi - update SPCR to aslc.

by evan.lloyd＠arm.com

From: Sami Mujawar <sami.mujawar(a)arm.com> Amend the Serial Port Console Redirection Table to enable (i.a.) Microsoft Windows Emergency Management Services (EMS) over the serial port. This patch replaces the Spcr.asl file which described the SPCR table in TDL format with Spcr.aslc which allows more flexibility by way of permitting the use of PCDs. This means the serial port usage can be modified at build. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Alexei Fedorov <alexei.fedorov(a)arm.com> Signed-off-by: Girish Pathak <girish.pathak(a)arm.com> Signed-off-by: Sami Mujawar <sami.mujawar(a)arm.com> Signed-off-by: Evan Lloyd <evan.lloyd(a)arm.com> --- Platforms/ARM/Juno/AcpiTables/AcpiTables.inf | 12 ++- Platforms/ARM/Juno/AcpiTables/Spcr.asl | 73 ------------------ Platforms/ARM/Juno/AcpiTables/Spcr.aslc | 79 ++++++++++++++++++++ Platforms/ARM/Juno/ArmJuno.dsc | 1 + 4 files changed, 90 insertions(+), 75 deletions(-) diff --git a/Platforms/ARM/Juno/AcpiTables/AcpiTables.inf b/Platforms/ARM/Juno/AcpiTables/AcpiTables.inf index 3159d7d..412f43d 100644 --- a/Platforms/ARM/Juno/AcpiTables/AcpiTables.inf +++ b/Platforms/ARM/Juno/AcpiTables/AcpiTables.inf @@ -2,7 +2,7 @@ # # ACPI table data and ASL sources required to boot the platform. # -# Copyright (c) 2014-2015, ARM Ltd. All rights reserved. +# Copyright (c) 2014-2016, ARM Ltd. All rights reserved. # # This program and the accompanying materials # are licensed and made available under the terms and conditions of the BSD License @@ -24,7 +24,7 @@ [Sources] Dsdt.asl Dbg2.asl - Spcr.asl + Spcr.aslc Facs.aslc Fadt.aslc Gtdt.aslc @@ -52,3 +52,11 @@ gArmTokenSpaceGuid.PcdGenericWatchdogControlBase gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase + + # + # PL011 UART Settings for Serial Port Console Redirection + # + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate + gArmPlatformTokenSpaceGuid.PL011UartClkInHz + gArmPlatformTokenSpaceGuid.PL011UartInterrupt diff --git a/Platforms/ARM/Juno/AcpiTables/Spcr.asl b/Platforms/ARM/Juno/AcpiTables/Spcr.asl deleted file mode 100644 index 2b65326..0000000 --- a/Platforms/ARM/Juno/AcpiTables/Spcr.asl +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Copyright (c) 2015, Graeme Gregory <graeme.gregory(a)linaro.org> - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED - * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - * NB: This License is also known as the "BSD 2-Clause License". - * - * - * [SPCR] ACPI Table - * - */ - -[0004] Signature : "SPCR" [Serial Port Console Redirection table] -[0004] Table Length : 00000050 -[0001] Revision : 02 -[0001] Checksum : 29 -[0006] Oem ID : "LINARO" -[0008] Oem Table ID : "ARM-JUNO" -[0004] Oem Revision : 00000000 -[0004] Asl Compiler ID : "INTL" -[0004] Asl Compiler Revision : 20140926 - -[0001] Interface Type : 03 -[0003] Reserved : 000000 - -[000C] Serial Port Register : [Generic Address Structure] -[0001] Space ID : 00 [SystemMemory] -[0001] Bit Width : 20 -[0001] Bit Offset : 00 -[0001] Encoded Access Width : 03 [DWord Access:32] -[0008] Address : 000000007FF80000 - -[0001] Interrupt Type : 08 -[0001] PCAT-compatible IRQ : 00 -[0004] Interrupt : 00000073 -[0001] Baud Rate : 07 -[0001] Parity : 00 -[0001] Stop Bits : 01 -[0001] Flow Control : 00 -[0001] Terminal Type : 03 -[0001] Reserved : 00 -[0002] PCI Device ID : FFFF -[0002] PCI Vendor ID : FFFF -[0001] PCI Bus : 00 -[0001] PCI Device : 00 -[0001] PCI Function : 00 -[0004] PCI Flags : 00000000 -[04Bh] PCI Segment : 00 -[04Ch] Reserved : 00000000 - diff --git a/Platforms/ARM/Juno/AcpiTables/Spcr.aslc b/Platforms/ARM/Juno/AcpiTables/Spcr.aslc new file mode 100644 index 0000000..d76f48a --- /dev/null +++ b/Platforms/ARM/Juno/AcpiTables/Spcr.aslc @@ -0,0 +1,79 @@ +/** @file +* SPCR Table +* +* Copyright (c) 2014 - 2016, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include "ArmPlatform.h" +#include <Library/AcpiLib.h> +#include <Library/ArmLib.h> +#include <Library/PcdLib.h> +#include <IndustryStandard/Acpi.h> +#include <IndustryStandard/SerialPortConsoleRedirectionTable.h> + +/** + * References: + * Serial Port Console Redirection Table Specification Version 1.03 - August 10, 2015 + **/ + + +/// +/// SPCR Flow Control +/// +#define SPCR_FLOW_CONTROL_NONE 0 + + +STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = { + ARM_ACPI_HEADER (EFI_ACPI_5_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE, + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE, + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION), + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_ARM_PL011_UART, + { + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE + }, + ARM_GAS32 (FixedPcdGet64 (PcdSerialRegisterBase)), + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC, + 0, // Not used on ARM + FixedPcdGet32 (PL011UartInterrupt), +#if (FixedPcdGet64 (PcdUartDefaultBaudRate) == 9600) + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_9600, +#elif (FixedPcdGet64 (PcdUartDefaultBaudRate) == 19200) + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_19200, +#elif (FixedPcdGet64 (PcdUartDefaultBaudRate) == 57600) + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_57600, +#elif (FixedPcdGet64 (PcdUartDefaultBaudRate) == 115200) + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200, +#else +#error Unsupported SPCR Baud Rate +#endif + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY, + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1, + SPCR_FLOW_CONTROL_NONE, + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI, + EFI_ACPI_RESERVED_BYTE, + 0xFFFF, + 0xFFFF, + 0x00, + 0x00, + 0x00, + 0x00000000, + 0x00, + EFI_ACPI_RESERVED_DWORD +}; + +// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Spcr; diff --git a/Platforms/ARM/Juno/ArmJuno.dsc b/Platforms/ARM/Juno/ArmJuno.dsc index d099d86..b718794 100644 --- a/Platforms/ARM/Juno/ArmJuno.dsc +++ b/Platforms/ARM/Juno/ArmJuno.dsc @@ -128,6 +128,7 @@ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200 gArmPlatformTokenSpaceGuid.PL011UartInteger|4 gArmPlatformTokenSpaceGuid.PL011UartFractional|0 + gArmPlatformTokenSpaceGuid.PL011UartInterrupt|115 ## PL031 RealTimeClock gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x1C170000 -- 2.7.0

8 years, 6 months

[RFC 00/20] Marvell Armada7040 SoC support

by Marcin Wojtas

Hello, Here's v4 version of the support. After thorough review of v3, this one comprise a lot of improvements. The major change is replacing support of obsolete SoC revisions with the newest one (A0). All the details can be found in a changelog below. As usually the patchset is available in the github: https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits/opp… Any comments or remarks would be welcome. Best regards, Marcin Changelog: v3 -> v4 * Update license messages - Unify - Add "Based on" statement were needed - Wrap every message at 80 characters - Add Marvell copyrights * Fix namings - All protocol/file names updated as suggested in review * Clean-up - Remove unneded blank lines and spaces - Fix typos * Add "Reviewed by" for currently accepted patches * Add support for new platform - Armada70x0 - Remove support for old platforms Apn806 and Armada7040_rz - Armada70x0 is based on Armada7040_rz with silicone fixes and improvements - No changes on drivers/libraries caused by this change - Update commit logs in whole tree * MppLib - Fix issue with writing to uninitialized memory * I2c and eeprom command - Remove dependency on BdsLibConnectAll call - I2c stack is connected only if eeprom command is executed and only in case it wasn't done before - gBS->ConnectController() used * BdsLib - Remove import of BdsLib - After rebase on top of new edk2, extra BdsLibConnectAll call isn't necessary (actually for now no BdsLibConnectAll is needed at all for our platform support) * sf command - Remove inclusion of relative path - Necessary macro now defined in globally exported file * RamDisk driver - Drop patch with this feature - As long as there is no possibility to format RamDisk with FAT, driver is not useful on Armada70x0 * fupdate command - Fix issue with "bad checksum" v2 -> v3 * Decrease binary size * Fupdate command - Remove regression - replace ShellExecute with RunShellCommand - Improve error paths * Add proper DEBUG library and change error print levels v1 -> v2 * Fix "may be used uninitialized" variables issue, branch compiles both with DEBUG and RELEASE flags * Remove I2C_FLAG_NORESTART dependency - replace it with local definition * Remove Marvell UART Library: - DW8250 IP has programming interface compatible with NS-16550. Since in edk2 there is support for 16550, internal library is unnecessary. - /Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf is used instead * RamDisk driver: - Remove old driver imported from EFI TOOLKIT 2.0 - Replace it with new MdeModulePkg/Universal/Disk/RamDiskDxe from edk2 - Lack of FAT formatting issue emerged * Add explicit dependency on IoLib in Drivers/Spi/SpiDxe.inf * Add poster's "Signed-off-by" registry to every commit message * Move to 05.04.2016 HEAD of edk2/master - Update CpuExceptionHandlerLib within OPP. Bartosz Szczepanek (3): Drivers/I2c: Create MvI2cDxe driver Drivers/I2c: Add MvEeprom driver Aplications/Eeprom: Add 'eeprom' command to shell Jan Dąbroś (15): Platforms/Marvell: Create MppLib Platforms/Marvell: Armada: Enable MppLib on Armada70x0 platform Platforms/Marvell: Enable I2C driver on Armada70x0 platform Plaforms/Marvell: Enable EEPROM driver on Armada70x0 platform Platforms/Marvell: Enable 'eeprom' command on Armada70x0 platform Platforms/Marvell: Add MARVELL_SPI_MASTER_PROTOCOL Drivers/Spi: Add Spi master driver Platforms/Marvell: Enable Spi master driver for Armada70x0 platform Platforms/Marvell: Add MARVELL_SPI_FLASH_PROTOCOL Drivers/Spi: Implement Spi flash driver Platforms/Marvell: Enable Spi flash driver for Armada70x0 platform Applications/SpiTool: Add 'sf' command utility Platforms/Marvell: Enable 'sf' command on Armada70x0 platform Applications/FirmwareUpdate: Add 'fupdate' comand to shell Platforms/Marvell: Enable 'fupdate' command on Armada70x0 platform Yehuda Yitschak (2): Platforms/Marvell: Add initial support for Armada70x0 SOC lib Platforms/Marvell: Add support for Armada70x0 platform Applications/EepromCmd/EepromCmd.c | 383 ++++++++++++ Applications/EepromCmd/EepromCmd.inf | 71 +++ Applications/EepromCmd/EepromCmd.uni | Bin 0 -> 6816 bytes Applications/FirmwareUpdate/FUpdate.c | 447 ++++++++++++++ Applications/FirmwareUpdate/FUpdate.inf | 68 ++ Applications/FirmwareUpdate/FUpdate.uni | Bin 0 -> 5838 bytes Applications/SpiTool/SpiFlashCmd.c | 526 ++++++++++++++++ Applications/SpiTool/SpiFlashCmd.inf | 75 +++ Applications/SpiTool/SpiFlashCmd.uni | Bin 0 -> 7216 bytes Documentation/Marvell/Drivers/EepromDriver.txt | 96 +++ Documentation/Marvell/Drivers/I2cDriver.txt | 64 ++ Documentation/Marvell/Drivers/SpiDriver.txt | 116 ++++ Documentation/Marvell/PortingGuide/I2c.txt | 16 + Documentation/Marvell/PortingGuide/Mpp.txt | 48 ++ Documentation/Marvell/PortingGuide/Spi.txt | 15 + Documentation/Marvell/PortingGuide/SpiFlash.txt | 19 + Drivers/I2c/Devices/MvEeprom/MvEeprom.c | 293 +++++++++ Drivers/I2c/Devices/MvEeprom/MvEeprom.h | 90 +++ Drivers/I2c/Devices/MvEeprom/MvEeprom.inf | 69 +++ Drivers/I2c/MvI2cDxe/MvI2cDxe.c | 683 +++++++++++++++++++++ Drivers/I2c/MvI2cDxe/MvI2cDxe.h | 258 ++++++++ Drivers/I2c/MvI2cDxe/MvI2cDxe.inf | 72 +++ Drivers/Spi/Devices/MvSpiFlash.c | 523 ++++++++++++++++ Drivers/Spi/Devices/MvSpiFlash.h | 130 ++++ Drivers/Spi/Devices/MvSpiFlash.inf | 66 ++ Drivers/Spi/MvSpiDxe.c | 378 ++++++++++++ Drivers/Spi/MvSpiDxe.h | 145 +++++ Drivers/Spi/MvSpiDxe.inf | 66 ++ Platforms/Marvell/Armada/Armada.dsc.inc | 459 ++++++++++++++ Platforms/Marvell/Armada/Armada70x0.dsc | 93 +++ Platforms/Marvell/Armada/Armada70x0.fdf | 273 ++++++++ .../Armada70x0Lib/AArch64/ArmPlatformHelper.S | 66 ++ .../Armada/Library/Armada70x0Lib/Armada70x0Lib.c | 155 +++++ .../Armada/Library/Armada70x0Lib/Armada70x0Lib.inf | 69 +++ .../Library/Armada70x0Lib/Armada70x0LibMem.c | 93 +++ Platforms/Marvell/Include/Library/MppLib.h | 42 ++ Platforms/Marvell/Include/Protocol/Eeprom.h | 60 ++ Platforms/Marvell/Include/Protocol/Spi.h | 105 ++++ Platforms/Marvell/Include/Protocol/SpiFlash.h | 113 ++++ Platforms/Marvell/Library/MppLib/MppLib.c | 161 +++++ Platforms/Marvell/Library/MppLib/MppLib.inf | 107 ++++ Platforms/Marvell/Marvell.dec | 132 ++++ 42 files changed, 6645 insertions(+) create mode 100644 Applications/EepromCmd/EepromCmd.c create mode 100644 Applications/EepromCmd/EepromCmd.inf create mode 100644 Applications/EepromCmd/EepromCmd.uni create mode 100644 Applications/FirmwareUpdate/FUpdate.c create mode 100644 Applications/FirmwareUpdate/FUpdate.inf create mode 100644 Applications/FirmwareUpdate/FUpdate.uni create mode 100644 Applications/SpiTool/SpiFlashCmd.c create mode 100644 Applications/SpiTool/SpiFlashCmd.inf create mode 100644 Applications/SpiTool/SpiFlashCmd.uni create mode 100644 Documentation/Marvell/Drivers/EepromDriver.txt create mode 100644 Documentation/Marvell/Drivers/I2cDriver.txt create mode 100644 Documentation/Marvell/Drivers/SpiDriver.txt create mode 100644 Documentation/Marvell/PortingGuide/I2c.txt create mode 100644 Documentation/Marvell/PortingGuide/Mpp.txt create mode 100644 Documentation/Marvell/PortingGuide/Spi.txt create mode 100644 Documentation/Marvell/PortingGuide/SpiFlash.txt create mode 100644 Drivers/I2c/Devices/MvEeprom/MvEeprom.c create mode 100644 Drivers/I2c/Devices/MvEeprom/MvEeprom.h create mode 100644 Drivers/I2c/Devices/MvEeprom/MvEeprom.inf create mode 100644 Drivers/I2c/MvI2cDxe/MvI2cDxe.c create mode 100644 Drivers/I2c/MvI2cDxe/MvI2cDxe.h create mode 100644 Drivers/I2c/MvI2cDxe/MvI2cDxe.inf create mode 100644 Drivers/Spi/Devices/MvSpiFlash.c create mode 100644 Drivers/Spi/Devices/MvSpiFlash.h create mode 100644 Drivers/Spi/Devices/MvSpiFlash.inf create mode 100644 Drivers/Spi/MvSpiDxe.c create mode 100644 Drivers/Spi/MvSpiDxe.h create mode 100644 Drivers/Spi/MvSpiDxe.inf create mode 100644 Platforms/Marvell/Armada/Armada.dsc.inc create mode 100644 Platforms/Marvell/Armada/Armada70x0.dsc create mode 100644 Platforms/Marvell/Armada/Armada70x0.fdf create mode 100644 Platforms/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelper.S create mode 100644 Platforms/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.c create mode 100644 Platforms/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf create mode 100644 Platforms/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c create mode 100644 Platforms/Marvell/Include/Library/MppLib.h create mode 100644 Platforms/Marvell/Include/Protocol/Eeprom.h create mode 100644 Platforms/Marvell/Include/Protocol/Spi.h create mode 100644 Platforms/Marvell/Include/Protocol/SpiFlash.h create mode 100644 Platforms/Marvell/Library/MppLib/MppLib.c create mode 100644 Platforms/Marvell/Library/MppLib/MppLib.inf create mode 100644 Platforms/Marvell/Marvell.dec -- 1.8.3.1

8 years, 6 months

[PATCH] Platforms/ARM: Juno: PL011 PCD changes

by evan.lloyd＠arm.com

From: Sami Mujawar <sami.mujawar(a)arm.com> The generic PL011 driver has been updated to allow for UARTs on a board having different clock sources (as is the case on Juno). This changes the Juno code to make use of the new driver options. The solution involves using the Baud rate and new PL011UartClkInHz PCDs to configure the UART ports. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Alexei Fedorov <alexei.fedorov(a)arm.com> Signed-off-by: Girish Pathak <girish.pathak(a)arm.com> Signed-off-by: Sami Mujawar <sami.mujawar(a)arm.com> Signed-off-by: Evan Lloyd <evan.lloyd(a)arm.com> --- Platforms/ARM/Juno/ArmJuno.dsc | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/Platforms/ARM/Juno/ArmJuno.dsc b/Platforms/ARM/Juno/ArmJuno.dsc index b718794..3e17831 100644 --- a/Platforms/ARM/Juno/ArmJuno.dsc +++ b/Platforms/ARM/Juno/ArmJuno.dsc @@ -126,8 +126,7 @@ ## PL011 - Serial Terminal gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x7FF80000 gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200 - gArmPlatformTokenSpaceGuid.PL011UartInteger|4 - gArmPlatformTokenSpaceGuid.PL011UartFractional|0 + gArmPlatformTokenSpaceGuid.PL011UartClkInHz|7372800 gArmPlatformTokenSpaceGuid.PL011UartInterrupt|115 ## PL031 RealTimeClock -- 2.7.0

8 years, 7 months

[PATCH] Platforms/ARM: get rid of A PRIORI declaration for Dxe/Pcd.inf

by Ard Biesheuvel

APRIORI declarations are evil. They force a driver to be dispatched before any other drivers, while completely ignoring normal precedence rules or protocol dependencies. In this particular case, the DXE version of Pcd.inf is loaded a priori to work around the problem that the default PcdLib resolution introduces a a protocol dependency on gPcdProtocolGuid, which provides dynamic PCD handling for other drivers, and is implemented by Pcd.inf. Since Pcd.inf depends on PcdLib as well, it can never be dispatched in the ordinary way if it inherits the default PcdLib resolution (since that will make it depend on itself), and so it must be made to depend on the Null implementation of PcdLib explicitly. So add this explicit override, and drop the A PRIORI declarations. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel(a)linaro.org> --- Note that the same reasoning applies to the PEI version of Pcd.inf, but we don't normally use that, and in fact, it already has a similar Null library class override in ArmVExpress-FVP-AArch64.dsc Platforms/ARM/Juno/ArmJuno.fdf | 4 ---- Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.fdf | 4 ---- Platforms/ARM/VExpress/ArmVExpress.dsc.inc | 5 ++++- 3 files changed, 4 insertions(+), 9 deletions(-) diff --git a/Platforms/ARM/Juno/ArmJuno.fdf b/Platforms/ARM/Juno/ArmJuno.fdf index a05151086910..3983c20de8e0 100644 --- a/Platforms/ARM/Juno/ArmJuno.fdf +++ b/Platforms/ARM/Juno/ArmJuno.fdf @@ -86,10 +86,6 @@ READ_LOCK_CAP = TRUE READ_LOCK_STATUS = TRUE FvNameGuid = B73FE497-B92E-416e-8326-45AD0D270092 - APRIORI DXE { - INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf - } - INF MdeModulePkg/Core/Dxe/DxeMain.inf INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf diff --git a/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.fdf b/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.fdf index 79c074c834d8..3bcdb1ca43f1 100644 --- a/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.fdf +++ b/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.fdf @@ -73,10 +73,6 @@ READ_LOCK_CAP = TRUE READ_LOCK_STATUS = TRUE FvNameGuid = 87940482-fc81-41c3-87e6-399cf85ac8a0 - APRIORI DXE { - INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf - } - INF MdeModulePkg/Core/Dxe/DxeMain.inf INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf diff --git a/Platforms/ARM/VExpress/ArmVExpress.dsc.inc b/Platforms/ARM/VExpress/ArmVExpress.dsc.inc index 9bb45c82a5e9..d898aef490f9 100644 --- a/Platforms/ARM/VExpress/ArmVExpress.dsc.inc +++ b/Platforms/ARM/VExpress/ArmVExpress.dsc.inc @@ -443,7 +443,10 @@ !endif [Components.common] - MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + MdeModulePkg/Universal/PCD/Dxe/Pcd.inf { + <LibraryClasses> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + } # Versatile Express FileSystem ArmPlatformPkg/FileSystem/BootMonFs/BootMonFs.inf -- 2.5.0

8 years, 7 months

[PATCH] Platforms/ARM: move FVP to unicore PrePi

by Ard Biesheuvel

Currently, the only supported way of running Tianocore on FVP is using ARM Trusted Firmware at EL3, in which case only a single core will enter the UEFI firmware at EL2. This means we can move to the UniCore flavor of PrePi/PrePeiCore, which now have been made compatible with running on an otherwise MpCore capable system. So replace the .inf references, and drop or update the PCDs related to secondary boot as appropriate. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel(a)linaro.org> --- Note that this depends on my patch 'ArmPlatformPkg/PrePi: allow unicore version to be used on MP hardware' http://article.gmane.org/gmane.comp.bios.edk2.devel/10903 Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc | 18 +++++------------- Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.fdf | 4 ++-- 2 files changed, 7 insertions(+), 15 deletions(-) diff --git a/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc b/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc index 78330d624216..92af088b7759 100644 --- a/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc +++ b/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc @@ -90,9 +90,8 @@ gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Fixed Virtual Platform" gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"ARM-FVP" - # Up to 8 cores on Base models. This works fine if model happens to have less. - gArmPlatformTokenSpaceGuid.PcdCoreCount|8 - gArmPlatformTokenSpaceGuid.PcdClusterCount|2 + # Only one core enters UEFI, and PSCI is implemented in EL3 by ATF + gArmPlatformTokenSpaceGuid.PcdCoreCount|1 # # NV Storage PCDs. Use base of 0x0C000000 for NOR1 @@ -106,18 +105,11 @@ gArmTokenSpaceGuid.PcdVFPEnabled|1 - # FVP models can have 2 clusters with 4 cpus each - # Stacks for MPCores in Secure World - # Trusted SRAM (DRAM on Foundation model) - gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0x04000000 - gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x1000 - gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize|0x800 - # Stacks for MPCores in Normal World # Non-Trusted SRAM gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x2E000000 gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x4000 - gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x1000 + gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x0 # System Memory (2GB - 16MB of Trusted DRAM at the top of the 32bit address space) gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000 @@ -213,14 +205,14 @@ # !ifdef EDK2_SKIP_PEICORE # UEFI is placed in RAM by bootloader - ArmPlatformPkg/PrePi/PeiMPCore.inf { + ArmPlatformPkg/PrePi/PeiUniCore.inf { <LibraryClasses> ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64Lib.inf ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf } !else # UEFI lives in FLASH and copies itself to RAM - ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf + ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf MdeModulePkg/Core/Pei/PeiMain.inf MdeModulePkg/Universal/PCD/Pei/Pcd.inf { <LibraryClasses> diff --git a/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.fdf b/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.fdf index 99230813b335..79c074c834d8 100644 --- a/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.fdf +++ b/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.fdf @@ -242,9 +242,9 @@ READ_LOCK_CAP = TRUE READ_LOCK_STATUS = TRUE !if $(EDK2_SKIP_PEICORE) == 1 - INF ArmPlatformPkg/PrePi/PeiMPCore.inf + INF ArmPlatformPkg/PrePi/PeiUniCore.inf !else - INF ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf + INF ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf INF MdeModulePkg/Core/Pei/PeiMain.inf INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf -- 2.5.0

8 years, 7 months

[PATCH] Platforms/ARM: Juno: HDLCD Graphics Output Protocol

by evan.lloyd＠arm.com

From: Sami Mujawar <sami.mujawar(a)arm.com> This patch enables the Graphics Output Protocol using HDLCD on the Juno platform. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Alexei Fedorov <alexei.fedorov(a)arm.com> Signed-off-by: Girish Pathak <girish.pathak(a)arm.com> Signed-off-by: Sami Mujawar <sami.mujawar(a)arm.com> Signed-off-by: Evan Lloyd <evan.lloyd(a)arm.com> --- Platforms/ARM/Juno/ArmJuno.dsc | 12 +++++++++++- Platforms/ARM/Juno/ArmJuno.fdf | 5 ++++- 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/Platforms/ARM/Juno/ArmJuno.dsc b/Platforms/ARM/Juno/ArmJuno.dsc index 02472ce..d099d86 100644 --- a/Platforms/ARM/Juno/ArmJuno.dsc +++ b/Platforms/ARM/Juno/ArmJuno.dsc @@ -1,5 +1,5 @@ # -# Copyright (c) 2013-2015, ARM Limited. All rights reserved. +# Copyright (c) 2013-2016, ARM Limited. All rights reserved. # # This program and the accompanying materials # are licensed and made available under the terms and conditions of the BSD License @@ -50,6 +50,8 @@ # USB Requirements UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf + LcdPlatformLib|ArmPlatformPkg/ArmJunoPkg/Library/HdLcdArmJunoLib/HdLcdArmJunoLib.inf + [LibraryClasses.ARM] ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf @@ -118,6 +120,9 @@ # ARM PrimeCell # + ## HdLcd + gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase|0x7FF60000 + ## PL011 - Serial Terminal gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x7FF80000 gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200 @@ -248,6 +253,11 @@ ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf # + # Graphic Output Protocol + # + ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcdGraphicsOutputDxe.inf + + # # Semi-hosting filesystem # ArmPkg/Filesystem/SemihostFs/SemihostFs.inf diff --git a/Platforms/ARM/Juno/ArmJuno.fdf b/Platforms/ARM/Juno/ArmJuno.fdf index e686a6d..2ca20b8 100644 --- a/Platforms/ARM/Juno/ArmJuno.fdf +++ b/Platforms/ARM/Juno/ArmJuno.fdf @@ -1,5 +1,5 @@ # -# Copyright (c) 2013-2015, ARM Limited. All rights reserved. +# Copyright (c) 2013-2016, ARM Limited. All rights reserved. # # This program and the accompanying materials # are licensed and made available under the terms and conditions of the BSD License @@ -135,6 +135,9 @@ FvNameGuid = B73FE497-B92E-416e-8326-45AD0D270092 # Versatile Express FileSystem INF ArmPlatformPkg/FileSystem/BootMonFs/BootMonFs.inf + # Graphic Output Protocol + INF ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcdGraphicsOutputDxe.inf + # # FAT filesystem + GPT/MBR partitioning # -- 2.7.0

8 years, 7 months

[PATCH] Override PrePeiCoreMPCore to allow 64-bit mailbox pointers

by Leo Duran

This patch supersedes PATCH 4/4 of the previous series. The path to the Override files is now correct. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran <leo.duran(a)amd.com> --- .../AMD/Styx/OverdriveBoard/OverdriveBoard.dsc | 2 +- .../AMD/Styx/OverdriveBoard/OverdriveBoard.fdf | 2 +- .../PrePeiCore/AArch64/ArchPrePeiCore.c | 58 +++++++ .../ArmPlatformPkg/PrePeiCore/AArch64/Exception.S | 126 ++++++++++++++++ .../ArmPlatformPkg/PrePeiCore/AArch64/Helper.S | 54 +++++++ .../PrePeiCore/AArch64/PrePeiCoreEntryPoint.S | 112 ++++++++++++++ .../PrePeiCore/AArch64/SwitchStack.S | 49 ++++++ .../ArmPlatformPkg/PrePeiCore/MainMPCore.c | 168 +++++++++++++++++++++ .../ArmPlatformPkg/PrePeiCore/PrePeiCore.c | 149 ++++++++++++++++++ .../ArmPlatformPkg/PrePeiCore/PrePeiCore.h | 85 +++++++++++ .../ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf | 76 ++++++++++ 11 files changed, 879 insertions(+), 2 deletions(-) create mode 100644 Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/ArchPrePeiCore.c create mode 100644 Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/Exception.S create mode 100644 Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/Helper.S create mode 100644 Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/PrePeiCoreEntryPoint.S create mode 100644 Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/SwitchStack.S create mode 100644 Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/MainMPCore.c create mode 100644 Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/PrePeiCore.c create mode 100644 Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/PrePeiCore.h create mode 100644 Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf diff --git a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc index e83a8ef..6ee7181 100644 --- a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc +++ b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc @@ -561,7 +561,7 @@ DEFINE TRANS_CODE = $(EL3_TO_EL2) !if $(DO_PSCI) ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf !else - ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf + OpenPlatformPkg/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf !endif MdeModulePkg/Core/Pei/PeiMain.inf MdeModulePkg/Universal/PCD/Pei/Pcd.inf { diff --git a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.fdf b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.fdf index cbfb6c3..0134af2 100644 --- a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.fdf +++ b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.fdf @@ -250,7 +250,7 @@ READ_LOCK_STATUS = TRUE !if $(DO_PSCI) INF ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf !else - INF ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf + INF OpenPlatformPkg/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf !endif INF MdeModulePkg/Core/Pei/PeiMain.inf INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf diff --git a/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/ArchPrePeiCore.c b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/ArchPrePeiCore.c new file mode 100644 index 0000000..9f86d3e --- /dev/null +++ b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/ArchPrePeiCore.c @@ -0,0 +1,58 @@ +/** @file +* Main file supporting the transition to PEI Core in Normal World for Versatile Express +* +* Copyright (c) 2012-2013, ARM Limited. All rights reserved. +* Copyright (c) 2016, AMD Inc. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ +/** + Unmodified from: + ArmPlatformPkg/PrePeiCore/AArch64/ArchPrePeiCore.c + +**/ + +#include <Library/PrintLib.h> +#include <Library/SerialPortLib.h> + +#include "PrePeiCore.h" + +VOID +PeiCommonExceptionEntry ( + IN UINT32 Entry, + IN UINTN LR + ) +{ + CHAR8 Buffer[100]; + UINTN CharCount; + + switch (Entry) { + case EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS: + CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Synchronous Exception at 0x%X\n\r", LR); + break; + case EXCEPT_AARCH64_IRQ: + CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"IRQ Exception at 0x%X\n\r", LR); + break; + case EXCEPT_AARCH64_FIQ: + CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"FIQ Exception at 0x%X\n\r", LR); + break; + case EXCEPT_AARCH64_SERROR: + CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"SError/Abort Exception at 0x%X\n\r", LR); + break; + default: + CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Unknown Exception at 0x%X\n\r", LR); + break; + } + + SerialPortWrite ((UINT8 *) Buffer, CharCount); + + while(1); +} + diff --git a/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/Exception.S b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/Exception.S new file mode 100644 index 0000000..38a4257 --- /dev/null +++ b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/Exception.S @@ -0,0 +1,126 @@ +# +# Copyright (c) 2011-2014, ARM Limited. All rights reserved. +# Copyright (c) 2016, AMD Inc. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# +#/** +# Unmodified from: +# ArmPlatformPkg/PrePeiCore/AArch64/Exception.S +# +#**/ + +#include <Chipset/AArch64.h> +#include <AsmMacroIoLibV8.h> +#include <Base.h> +#include <AutoGen.h> + +.text + +//============================================================ +//Default Exception Handlers +//============================================================ + +#define TO_HANDLER \ + EL1_OR_EL2(x1) \ +1: mrs x1, elr_el1 /* EL1 Exception Link Register */ ;\ + b 3f ;\ +2: mrs x1, elr_el2 /* EL2 Exception Link Register */ ;\ +3: bl ASM_PFX(PeiCommonExceptionEntry) ; + + +// +// Default Exception handlers: There is no plan to return from any of these exceptions. +// No context saving at all. +// + +VECTOR_BASE(PeiVectorTable) + +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SP0_SYNC) +_DefaultSyncExceptHandler_t: + mov x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS + TO_HANDLER + +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SP0_IRQ) +_DefaultIrq_t: + mov x0, #EXCEPT_AARCH64_IRQ + TO_HANDLER + +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SP0_FIQ) +_DefaultFiq_t: + mov x0, #EXCEPT_AARCH64_FIQ + TO_HANDLER + +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SP0_SERR) +_DefaultSError_t: + mov x0, #EXCEPT_AARCH64_SERROR + TO_HANDLER + +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPx_SYNC) +_DefaultSyncExceptHandler_h: + mov x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS + TO_HANDLER + +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPx_IRQ) +_DefaultIrq_h: + mov x0, #EXCEPT_AARCH64_IRQ + TO_HANDLER + +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPx_FIQ) +_DefaultFiq_h: + mov x0, #EXCEPT_AARCH64_FIQ + TO_HANDLER + +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPx_SERR) +_DefaultSError_h: + mov x0, #EXCEPT_AARCH64_SERROR + TO_HANDLER + +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A64_SYNC) +_DefaultSyncExceptHandler_LowerA64: + mov x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS + TO_HANDLER + +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A64_IRQ) +_DefaultIrq_LowerA64: + mov x0, #EXCEPT_AARCH64_IRQ + TO_HANDLER + +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A64_FIQ) +_DefaultFiq_LowerA64: + mov x0, #EXCEPT_AARCH64_FIQ + TO_HANDLER + +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A64_SERR) +_DefaultSError_LowerA64: + mov x0, #EXCEPT_AARCH64_SERROR + TO_HANDLER + +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A32_SYNC) +_DefaultSyncExceptHandler_LowerA32: + mov x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS + TO_HANDLER + +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A32_IRQ) +_DefaultIrq_LowerA32: + mov x0, #EXCEPT_AARCH64_IRQ + TO_HANDLER + +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A32_FIQ) +_DefaultFiq_LowerA32: + mov x0, #EXCEPT_AARCH64_FIQ + TO_HANDLER + +VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A32_SERR) +_DefaultSError_LowerA32: + mov x0, #EXCEPT_AARCH64_SERROR + TO_HANDLER + +VECTOR_END(PeiVectorTable) diff --git a/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/Helper.S b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/Helper.S new file mode 100644 index 0000000..b9a0049 --- /dev/null +++ b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/Helper.S @@ -0,0 +1,54 @@ +#======================================================================================== +# Copyright (c) 2011-2013, ARM Limited. All rights reserved. +# Copyright (c) 2016, AMD Inc. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http:#opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#======================================================================================= +#/** +# Unmodified from: +# ArmPlatformPkg/PrePeiCore/AArch64/Helper.S +# +#**/ + +#include <AsmMacroIoLibV8.h> +#include <Chipset/AArch64.h> + +#start of the code section +.text +.align 3 + +GCC_ASM_EXPORT(SetupExceptionLevel1) +GCC_ASM_EXPORT(SetupExceptionLevel2) + +// Setup EL1 while in EL1 +ASM_PFX(SetupExceptionLevel1): + mov x5, x30 // Save LR + + mov x0, #CPACR_CP_FULL_ACCESS + bl ASM_PFX(ArmWriteCpacr) // Disable copro traps to EL1 + + ret x5 + +// Setup EL2 while in EL2 +ASM_PFX(SetupExceptionLevel2): + msr sctlr_el2, xzr + mrs x0, hcr_el2 // Read EL2 Hypervisor configuration Register + + // Send all interrupts to their respective Exception levels for EL2 + orr x0, x0, #(1 << 3) // Enable EL2 FIQ + orr x0, x0, #(1 << 4) // Enable EL2 IRQ + orr x0, x0, #(1 << 5) // Enable EL2 SError and Abort + msr hcr_el2, x0 // Write back our settings + + msr cptr_el2, xzr // Disable copro traps to EL2 + + ret + +ASM_FUNCTION_REMOVE_IF_UNREFERENCED diff --git a/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/PrePeiCoreEntryPoint.S b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/PrePeiCoreEntryPoint.S new file mode 100644 index 0000000..2ddf4d4 --- /dev/null +++ b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/PrePeiCoreEntryPoint.S @@ -0,0 +1,112 @@ +// +// Copyright (c) 2011-2014, ARM Limited. All rights reserved. +// Copyright (c) 2016, AMD Inc. All rights reserved. +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// + +#/** +# Unmodified from: +# ArmPlatformPkg/PrePeiCore/AArch64/PrePeiCoreEntryPoint.S +# +#**/ + +#include <AsmMacroIoLibV8.h> +#include <Base.h> +#include <Library/PcdLib.h> +#include <AutoGen.h> + +.text +.align 3 + +GCC_ASM_IMPORT(CEntryPoint) +GCC_ASM_IMPORT(ArmPlatformGetCorePosition) +GCC_ASM_IMPORT(ArmPlatformIsPrimaryCore) +GCC_ASM_IMPORT(ArmReadMpidr) +GCC_ASM_IMPORT(ArmPlatformPeiBootAction) +GCC_ASM_EXPORT(_ModuleEntryPoint) + +StartupAddr: .8byte CEntryPoint + +ASM_PFX(_ModuleEntryPoint): + // Do early platform specific actions + bl ASM_PFX(ArmPlatformPeiBootAction) + +// NOTE: We could be booting from EL3, EL2 or EL1. Need to correctly detect +// and configure the system accordingly. EL2 is default if possible. +// If we started in EL3 we need to switch and run at EL2. +// If we are running at EL2 stay in EL2 +// If we are starting at EL1 stay in EL1. + +// If started at EL3 Sec is run and switches to EL2 before jumping to PEI. +// If started at EL1 or EL2 Sec jumps directly to PEI without making any +// changes. + +// Which EL are we running at? Every EL needs some level of setup... +// We should not run this code in EL3 + EL1_OR_EL2(x0) +1:bl ASM_PFX(SetupExceptionLevel1) + b ASM_PFX(MainEntryPoint) +2:bl ASM_PFX(SetupExceptionLevel2) + b ASM_PFX(MainEntryPoint) + +ASM_PFX(MainEntryPoint): + // Identify CPU ID + bl ASM_PFX(ArmReadMpidr) + // Keep a copy of the MpId register value + mov x5, x0 + + // Is it the Primary Core ? + bl ASM_PFX(ArmPlatformIsPrimaryCore) + + // Get the top of the primary stacks (and the base of the secondary stacks) + LoadConstantToReg (FixedPcdGet64(PcdCPUCoresStackBase), x1) + LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), x2) + add x1, x1, x2 + + // x0 is equal to 1 if I am the primary core + cmp x0, #1 + b.eq _SetupPrimaryCoreStack + +_SetupSecondaryCoreStack: + // x1 contains the base of the secondary stacks + + // Get the Core Position + mov x6, x1 // Save base of the secondary stacks + mov x0, x5 + bl ASM_PFX(ArmPlatformGetCorePosition) + // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack + add x0, x0, #1 + + // StackOffset = CorePos * StackSize + LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), x2) + mul x0, x0, x2 + // SP = StackBase + StackOffset + add sp, x6, x0 + +_PrepareArguments: + // The PEI Core Entry Point has been computed by GenFV and stored in the second entry of the Reset Vector + LoadConstantToReg (FixedPcdGet64(PcdFvBaseAddress), x2) + add x2, x2, #8 + ldr x1, [x2] + + // Move sec startup address into a data register + // Ensure we're jumping to FV version of the code (not boot remapped alias) + ldr x3, StartupAddr + + // Jump to PrePeiCore C code + // x0 = mp_id + // x1 = pei_core_address + mov x0, x5 + blr x3 + +_SetupPrimaryCoreStack: + mov sp, x1 + b _PrepareArguments diff --git a/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/SwitchStack.S b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/SwitchStack.S new file mode 100644 index 0000000..8414d29 --- /dev/null +++ b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/SwitchStack.S @@ -0,0 +1,49 @@ +#------------------------------------------------------------------------------ +# +# Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR> +# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> +# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR> +# Copyright (c) 2016, AMD Inc. All rights reserved.<BR> +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php. +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#------------------------------------------------------------------------------ +#/** +# Unmodified from: +# ArmPlatformPkg/PrePeiCore/AArch64/SwitchStack.S +# +#**/ + +.text +.align 3 + +GCC_ASM_EXPORT(SecSwitchStack) + + + +#/** +# This allows the caller to switch the stack and return +# +# @param StackDelta Signed amount by which to modify the stack pointer +# +# @return Nothing. Goes to the Entry Point passing in the new parameters +# +#**/ +#VOID +#EFIAPI +#SecSwitchStack ( +# VOID *StackDelta +# )# +# +ASM_PFX(SecSwitchStack): + mov x1, sp + add x1, x0, x1 + mov sp, x1 + ret + diff --git a/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/MainMPCore.c b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/MainMPCore.c new file mode 100644 index 0000000..c708f84 --- /dev/null +++ b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/MainMPCore.c @@ -0,0 +1,168 @@ +/** @file +* +* Copyright (c) 2011-2014, ARM Limited. All rights reserved. +* Copyright (c) 2016, AMD Inc. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ +/** + Derived from: + ArmPlatformPkg/PrePeiCore/MainMPCore.c + + Adds MmioWrite64() for 64-bit mailbox pointers. + +**/ + +#include <Library/ArmGicLib.h> + +#include <Ppi/ArmMpCoreInfo.h> + +#include "PrePeiCore.h" + +/* + * This is the main function for secondary cores. They loop around until a non Null value is written to + * SYS_FLAGS register.The SYS_FLAGS register is platform specific. + * Note:The secondary cores, while executing secondary_main, assumes that: + * : SGI 0 is configured as Non-secure interrupt + * : Priority Mask is configured to allow SGI 0 + * : Interrupt Distributor and CPU interfaces are enabled + * + */ +VOID +EFIAPI +SecondaryMain ( + IN UINTN MpId + ) +{ + EFI_STATUS Status; + UINTN PpiListSize; + UINTN PpiListCount; + EFI_PEI_PPI_DESCRIPTOR *PpiList; + ARM_MP_CORE_INFO_PPI *ArmMpCoreInfoPpi; + UINTN Index; + UINTN ArmCoreCount; + ARM_CORE_INFO *ArmCoreInfoTable; + UINT32 ClusterId; + UINT32 CoreId; + VOID (*SecondaryStart)(VOID); + UINTN SecondaryEntryAddr; + UINTN AcknowledgeInterrupt; + UINTN InterruptId; + + ClusterId = GET_CLUSTER_ID(MpId); + CoreId = GET_CORE_ID(MpId); + + // Get the gArmMpCoreInfoPpiGuid + PpiListSize = 0; + ArmPlatformGetPlatformPpiList (&PpiListSize, &PpiList); + PpiListCount = PpiListSize / sizeof(EFI_PEI_PPI_DESCRIPTOR); + for (Index = 0; Index < PpiListCount; Index++, PpiList++) { + if (CompareGuid (PpiList->Guid, &gArmMpCoreInfoPpiGuid) == TRUE) { + break; + } + } + + // On MP Core Platform we must implement the ARM MP Core Info PPI + ASSERT (Index != PpiListCount); + + ArmMpCoreInfoPpi = PpiList->Ppi; + ArmCoreCount = 0; + Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable); + ASSERT_EFI_ERROR (Status); + + // Find the core in the ArmCoreTable + for (Index = 0; Index < ArmCoreCount; Index++) { + if ((ArmCoreInfoTable[Index].ClusterId == ClusterId) && (ArmCoreInfoTable[Index].CoreId == CoreId)) { + break; + } + } + + // The ARM Core Info Table must define every core + ASSERT (Index != ArmCoreCount); + + // Clear Secondary cores MailBox + if (sizeof(UINTN) == sizeof(UINT64)) + MmioWrite64 (ArmCoreInfoTable[Index].MailboxClearAddress, ArmCoreInfoTable[Index].MailboxClearValue); + else + MmioWrite32 (ArmCoreInfoTable[Index].MailboxClearAddress, ArmCoreInfoTable[Index].MailboxClearValue); + + do { + ArmCallWFI (); + + // Read the Mailbox + if (sizeof(UINTN) == sizeof(UINT64)) + SecondaryEntryAddr = MmioRead64 (ArmCoreInfoTable[Index].MailboxGetAddress); + else + SecondaryEntryAddr = MmioRead32 (ArmCoreInfoTable[Index].MailboxGetAddress); + + // Acknowledge the interrupt and send End of Interrupt signal. + AcknowledgeInterrupt = ArmGicAcknowledgeInterrupt (PcdGet32 (PcdGicInterruptInterfaceBase), &InterruptId); + // Check if it is a valid interrupt ID + if (InterruptId < ArmGicGetMaxNumInterrupts (PcdGet32 (PcdGicDistributorBase))) { + // Got a valid SGI number hence signal End of Interrupt + ArmGicEndOfInterrupt (PcdGet32 (PcdGicInterruptInterfaceBase), AcknowledgeInterrupt); + } + } while (SecondaryEntryAddr == 0); + + // Jump to secondary core entry point. + SecondaryStart = (VOID (*)())SecondaryEntryAddr; + SecondaryStart(); + + // The secondaries shouldn't reach here + ASSERT(FALSE); +} + +VOID +EFIAPI +PrimaryMain ( + IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint + ) +{ + EFI_SEC_PEI_HAND_OFF SecCoreData; + UINTN PpiListSize; + EFI_PEI_PPI_DESCRIPTOR *PpiList; + UINTN TemporaryRamBase; + UINTN TemporaryRamSize; + + CreatePpiList (&PpiListSize, &PpiList); + + // Enable the GIC Distributor + ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase)); + + // If ArmVe has not been built as Standalone then we need to wake up the secondary cores + if (FeaturePcdGet (PcdSendSgiToBringUpSecondaryCores)) { + // Sending SGI to all the Secondary CPU interfaces + ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId)); + } + + // Adjust the Temporary Ram as the new Ppi List (Common + Platform Ppi Lists) is created at + // the base of the primary core stack + PpiListSize = ALIGN_VALUE(PpiListSize, CPU_STACK_ALIGNMENT); + TemporaryRamBase = (UINTN)PcdGet64 (PcdCPUCoresStackBase) + PpiListSize; + TemporaryRamSize = (UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize) - PpiListSize; + + // + // Bind this information into the SEC hand-off state + // Note: this must be in sync with the stuff in the asm file + // Note also: HOBs (pei temp ram) MUST be above stack + // + SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF); + SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet64 (PcdFvBaseAddress); + SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdFvSize); + SecCoreData.TemporaryRamBase = (VOID *)TemporaryRamBase; // We run on the primary core (and so we use the first stack) + SecCoreData.TemporaryRamSize = TemporaryRamSize; + SecCoreData.PeiTemporaryRamBase = SecCoreData.TemporaryRamBase; + SecCoreData.PeiTemporaryRamSize = ALIGN_VALUE (SecCoreData.TemporaryRamSize / 2, CPU_STACK_ALIGNMENT); + SecCoreData.StackBase = (VOID *)((UINTN)SecCoreData.TemporaryRamBase + SecCoreData.PeiTemporaryRamSize); + SecCoreData.StackSize = (TemporaryRamBase + TemporaryRamSize) - (UINTN)SecCoreData.StackBase; + + // Jump to PEI core entry point + PeiCoreEntryPoint (&SecCoreData, PpiList); +} diff --git a/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/PrePeiCore.c b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/PrePeiCore.c new file mode 100644 index 0000000..7b45c00 --- /dev/null +++ b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/PrePeiCore.c @@ -0,0 +1,149 @@ +/** @file +* Main file supporting the transition to PEI Core in Normal World for Versatile Express +* +* Copyright (c) 2011-2014, ARM Limited. All rights reserved. +* Copyright (c) 2016, AMD Inc. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ +/** + Unmodified from: + ArmPlatformPkg/PrePeiCore/PrePeiCore.c + +**/ + +#include <Library/BaseLib.h> +#include <Library/DebugAgentLib.h> +#include <Library/ArmLib.h> + +#include "PrePeiCore.h" + +CONST EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI mTemporaryRamSupportPpi = { PrePeiCoreTemporaryRamSupport }; + +CONST EFI_PEI_PPI_DESCRIPTOR gCommonPpiTable[] = { + { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &gEfiTemporaryRamSupportPpiGuid, + (VOID *) &mTemporaryRamSupportPpi + } +}; + +VOID +CreatePpiList ( + OUT UINTN *PpiListSize, + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList + ) +{ + EFI_PEI_PPI_DESCRIPTOR *PlatformPpiList; + UINTN PlatformPpiListSize; + UINTN ListBase; + EFI_PEI_PPI_DESCRIPTOR *LastPpi; + + // Get the Platform PPIs + PlatformPpiListSize = 0; + ArmPlatformGetPlatformPpiList (&PlatformPpiListSize, &PlatformPpiList); + + // Copy the Common and Platform PPis in Temporrary Memory + ListBase = PcdGet64 (PcdCPUCoresStackBase); + CopyMem ((VOID*)ListBase, gCommonPpiTable, sizeof(gCommonPpiTable)); + CopyMem ((VOID*)(ListBase + sizeof(gCommonPpiTable)), PlatformPpiList, PlatformPpiListSize); + + // Set the Terminate flag on the last PPI entry + LastPpi = (EFI_PEI_PPI_DESCRIPTOR*)ListBase + ((sizeof(gCommonPpiTable) + PlatformPpiListSize) / sizeof(EFI_PEI_PPI_DESCRIPTOR)) - 1; + LastPpi->Flags |= EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST; + + *PpiList = (EFI_PEI_PPI_DESCRIPTOR*)ListBase; + *PpiListSize = sizeof(gCommonPpiTable) + PlatformPpiListSize; +} + +VOID +CEntryPoint ( + IN UINTN MpId, + IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint + ) +{ + // Data Cache enabled on Primary core when MMU is enabled. + ArmDisableDataCache (); + // Invalidate Data cache + ArmInvalidateDataCache (); + // Invalidate instruction cache + ArmInvalidateInstructionCache (); + // Enable Instruction Caches on all cores. + ArmEnableInstructionCache (); + + // + // Note: Doesn't have to Enable CPU interface in non-secure world, + // as Non-secure interface is already enabled in Secure world. + // + + // Write VBAR - The Exception Vector table must be aligned to its requirement + // Note: The AArch64 Vector table must be 2k-byte aligned - if this assertion fails ensure + // 'Align=4K' is defined into your FDF for this module. + ASSERT (((UINTN)PeiVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0); + ArmWriteVBar ((UINTN)PeiVectorTable); + + //Note: The MMU will be enabled by MemoryPeim. Only the primary core will have the MMU on. + + // If not primary Jump to Secondary Main + if (ArmPlatformIsPrimaryCore (MpId)) { + // Initialize the Debug Agent for Source Level Debugging + InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL); + SaveAndSetDebugTimerInterrupt (TRUE); + + // Initialize the platform specific controllers + ArmPlatformInitialize (MpId); + + // Goto primary Main. + PrimaryMain (PeiCoreEntryPoint); + } else { + SecondaryMain (MpId); + } + + // PEI Core should always load and never return + ASSERT (FALSE); +} + +EFI_STATUS +EFIAPI +PrePeiCoreTemporaryRamSupport ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase, + IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase, + IN UINTN CopySize + ) +{ + VOID *OldHeap; + VOID *NewHeap; + VOID *OldStack; + VOID *NewStack; + UINTN HeapSize; + + HeapSize = ALIGN_VALUE (CopySize / 2, CPU_STACK_ALIGNMENT); + + OldHeap = (VOID*)(UINTN)TemporaryMemoryBase; + NewHeap = (VOID*)((UINTN)PermanentMemoryBase + (CopySize - HeapSize)); + + OldStack = (VOID*)((UINTN)TemporaryMemoryBase + HeapSize); + NewStack = (VOID*)(UINTN)PermanentMemoryBase; + + // + // Migrate the temporary memory stack to permanent memory stack. + // + CopyMem (NewStack, OldStack, CopySize - HeapSize); + + // + // Migrate the temporary memory heap to permanent memory heap. + // + CopyMem (NewHeap, OldHeap, HeapSize); + + SecSwitchStack ((UINTN)NewStack - (UINTN)OldStack); + + return EFI_SUCCESS; +} diff --git a/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/PrePeiCore.h b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/PrePeiCore.h new file mode 100644 index 0000000..334f086 --- /dev/null +++ b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/PrePeiCore.h @@ -0,0 +1,85 @@ +/** @file +* Main file supporting the transition to PEI Core in Normal World for Versatile Express +* +* Copyright (c) 2011, ARM Limited. All rights reserved. +* Copyright (c) 2016, AMD Inc. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ +/** + Unmodified from: + ArmPlatformPkg/PrePeiCore/PrePeiCore.h + +**/ + +#ifndef __PREPEICORE_H_ +#define __PREPEICORE_H_ + +#include <Library/ArmLib.h> +#include <Library/ArmPlatformLib.h> +#include <Library/BaseMemoryLib.h> +#include <Library/DebugLib.h> +#include <Library/IoLib.h> +#include <Library/PcdLib.h> + +#include <PiPei.h> +#include <Ppi/TemporaryRamSupport.h> + +VOID +CreatePpiList ( + OUT UINTN *PpiListSize, + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList + ); + +EFI_STATUS +EFIAPI +PrePeiCoreTemporaryRamSupport ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase, + IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase, + IN UINTN CopySize + ); + +VOID +SecSwitchStack ( + INTN StackDelta + ); + +// Vector Table for Pei Phase +VOID PeiVectorTable (VOID); + +VOID +EFIAPI +PrimaryMain ( + IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint + ); + +/* + * This is the main function for secondary cores. They loop around until a non Null value is written to + * SYS_FLAGS register.The SYS_FLAGS register is platform specific. + * Note:The secondary cores, while executing secondary_main, assumes that: + * : SGI 0 is configured as Non-secure interrupt + * : Priority Mask is configured to allow SGI 0 + * : Interrupt Distributor and CPU interfaces are enabled + * + */ +VOID +EFIAPI +SecondaryMain ( + IN UINTN MpId + ); + +VOID +PeiCommonExceptionEntry ( + IN UINT32 Entry, + IN UINTN LR + ); + +#endif diff --git a/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf new file mode 100644 index 0000000..28b5b04 --- /dev/null +++ b/Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf @@ -0,0 +1,76 @@ +#/** @file +# Pre PeiCore - Hand-off to PEI Core in Normal World +# +# Copyright (c) 2011-2014, ARM Limited. All rights reserved. +# Copyright (c) 2016, AMD Inc. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ +#/** +# Derived from: +# ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf +# +# Removes [Sources.ARM] section +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = ArmPlatformPrePeiCore + FILE_GUID = 469fc080-aec1-11df-927c-0002a5d5c51b + MODULE_TYPE = SEC + VERSION_STRING = 1.0 + +[Sources.common] + MainMPCore.c + PrePeiCore.c + +[Sources.AARCH64] + AArch64/ArchPrePeiCore.c + AArch64/PrePeiCoreEntryPoint.S + AArch64/SwitchStack.S + AArch64/Exception.S + AArch64/Helper.S + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + +[LibraryClasses] + ArmLib + ArmPlatformLib + BaseLib + DebugLib + DebugAgentLib + IoLib + ArmGicLib + PrintLib + SerialPortLib + +[Ppis] + gEfiTemporaryRamSupportPpiGuid + gArmMpCoreInfoPpiGuid + +[FeaturePcd] + gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores + +[FixedPcd] + gArmTokenSpaceGuid.PcdFvBaseAddress + gArmTokenSpaceGuid.PcdFvSize + + gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase + gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize + gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize + + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase + gArmTokenSpaceGuid.PcdGicSgiIntId -- 1.9.1

8 years, 7 months

[PATCH 0/4] Styx: Clean-up and remove dependencies

by Leo Duran

Leo Duran (4): Support only ACPI+PSCI on HuskyBoard Override to invoke BdsLibConnectAll() no longer necesasary Move FdtBlob and FdtDxe under OverdriveBoard Override PrePeiCoreMPCore to allow 64-bit mailbox pointers .../Styx/Drivers/FdtDxe/AArch64/BdsLinuxLoader.c | 122 ---- .../Drivers/FdtDxe/AArch64/BdsLinuxLoaderHelper.S | 87 --- Platforms/AMD/Styx/Drivers/FdtDxe/BdsLinuxFdt.c | 754 --------------------- Platforms/AMD/Styx/Drivers/FdtDxe/FdtDxe.c | 279 -------- Platforms/AMD/Styx/Drivers/FdtDxe/FdtDxe.h | 55 -- Platforms/AMD/Styx/Drivers/FdtDxe/FdtDxe.inf | 90 --- Platforms/AMD/Styx/Drivers/FdtDxe/LinuxLoader.h | 166 ----- .../AMD/Styx/Drivers/FdtDxe/LinuxLoaderHelper.c | 192 ------ Platforms/AMD/Styx/FdtBlob/styx-husky.dtb | Bin 8093 -> 0 bytes Platforms/AMD/Styx/FdtBlob/styx-husky.dts | 435 ------------ Platforms/AMD/Styx/FdtBlob/styx-overdrive.dtb | Bin 8089 -> 0 bytes Platforms/AMD/Styx/FdtBlob/styx-overdrive.dts | 435 ------------ Platforms/AMD/Styx/HuskyBoard/HuskyBoard.dsc | 12 +- Platforms/AMD/Styx/HuskyBoard/HuskyBoard.fdf | 13 - .../AMD/Styx/OverdriveBoard/FdtBlob/styx-husky.dtb | Bin 0 -> 8093 bytes .../AMD/Styx/OverdriveBoard/FdtBlob/styx-husky.dts | 435 ++++++++++++ .../Styx/OverdriveBoard/FdtBlob/styx-overdrive.dtb | Bin 0 -> 8089 bytes .../Styx/OverdriveBoard/FdtBlob/styx-overdrive.dts | 435 ++++++++++++ .../OverdriveBoard/FdtDxe/AArch64/BdsLinuxLoader.c | 122 ++++ .../FdtDxe/AArch64/BdsLinuxLoaderHelper.S | 87 +++ .../AMD/Styx/OverdriveBoard/FdtDxe/BdsLinuxFdt.c | 754 +++++++++++++++++++++ Platforms/AMD/Styx/OverdriveBoard/FdtDxe/FdtDxe.c | 279 ++++++++ Platforms/AMD/Styx/OverdriveBoard/FdtDxe/FdtDxe.h | 55 ++ .../AMD/Styx/OverdriveBoard/FdtDxe/FdtDxe.inf | 90 +++ .../AMD/Styx/OverdriveBoard/FdtDxe/LinuxLoader.h | 166 +++++ .../Styx/OverdriveBoard/FdtDxe/LinuxLoaderHelper.c | 192 ++++++ .../AMD/Styx/OverdriveBoard/OverdriveBoard.dsc | 6 +- .../AMD/Styx/OverdriveBoard/OverdriveBoard.fdf | 6 +- .../PrePeiCore/AArch64/ArchPrePeiCore.c | 58 ++ .../ArmPlatformPkg/PrePeiCore/AArch64/Exception.S | 126 ++++ .../ArmPlatformPkg/PrePeiCore/AArch64/Helper.S | 54 ++ .../PrePeiCore/AArch64/PrePeiCoreEntryPoint.S | 112 +++ .../PrePeiCore/AArch64/SwitchStack.S | 49 ++ .../ArmPlatformPkg/PrePeiCore/MainMPCore.c | 168 +++++ .../ArmPlatformPkg/PrePeiCore/PrePeiCore.c | 149 ++++ .../ArmPlatformPkg/PrePeiCore/PrePeiCore.h | 85 +++ .../ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf | 76 +++ .../Library/PlatformIntelBdsLib/IntelBdsPlatform.c | 377 ----------- .../Library/PlatformIntelBdsLib/IntelBdsPlatform.h | 35 - .../PlatformIntelBdsLib/PlatformIntelBdsLib.inf | 62 -- 40 files changed, 3499 insertions(+), 3119 deletions(-) delete mode 100644 Platforms/AMD/Styx/Drivers/FdtDxe/AArch64/BdsLinuxLoader.c delete mode 100644 Platforms/AMD/Styx/Drivers/FdtDxe/AArch64/BdsLinuxLoaderHelper.S delete mode 100644 Platforms/AMD/Styx/Drivers/FdtDxe/BdsLinuxFdt.c delete mode 100644 Platforms/AMD/Styx/Drivers/FdtDxe/FdtDxe.c delete mode 100644 Platforms/AMD/Styx/Drivers/FdtDxe/FdtDxe.h delete mode 100644 Platforms/AMD/Styx/Drivers/FdtDxe/FdtDxe.inf delete mode 100644 Platforms/AMD/Styx/Drivers/FdtDxe/LinuxLoader.h delete mode 100644 Platforms/AMD/Styx/Drivers/FdtDxe/LinuxLoaderHelper.c delete mode 100644 Platforms/AMD/Styx/FdtBlob/styx-husky.dtb delete mode 100644 Platforms/AMD/Styx/FdtBlob/styx-husky.dts delete mode 100644 Platforms/AMD/Styx/FdtBlob/styx-overdrive.dtb delete mode 100644 Platforms/AMD/Styx/FdtBlob/styx-overdrive.dts create mode 100644 Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-husky.dtb create mode 100644 Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-husky.dts create mode 100644 Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dtb create mode 100644 Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dts create mode 100644 Platforms/AMD/Styx/OverdriveBoard/FdtDxe/AArch64/BdsLinuxLoader.c create mode 100644 Platforms/AMD/Styx/OverdriveBoard/FdtDxe/AArch64/BdsLinuxLoaderHelper.S create mode 100644 Platforms/AMD/Styx/OverdriveBoard/FdtDxe/BdsLinuxFdt.c create mode 100644 Platforms/AMD/Styx/OverdriveBoard/FdtDxe/FdtDxe.c create mode 100644 Platforms/AMD/Styx/OverdriveBoard/FdtDxe/FdtDxe.h create mode 100644 Platforms/AMD/Styx/OverdriveBoard/FdtDxe/FdtDxe.inf create mode 100644 Platforms/AMD/Styx/OverdriveBoard/FdtDxe/LinuxLoader.h create mode 100644 Platforms/AMD/Styx/OverdriveBoard/FdtDxe/LinuxLoaderHelper.c create mode 100644 Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/ArchPrePeiCore.c create mode 100644 Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/Exception.S create mode 100644 Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/Helper.S create mode 100644 Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/PrePeiCoreEntryPoint.S create mode 100644 Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/AArch64/SwitchStack.S create mode 100644 Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/MainMPCore.c create mode 100644 Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/PrePeiCore.c create mode 100644 Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/PrePeiCore.h create mode 100644 Platforms/AMD/Styx/OverdriveBoard/Override/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf delete mode 100644 Platforms/AMD/Styx/Override/ArmPlatformPkg/Library/PlatformIntelBdsLib/IntelBdsPlatform.c delete mode 100644 Platforms/AMD/Styx/Override/ArmPlatformPkg/Library/PlatformIntelBdsLib/IntelBdsPlatform.h delete mode 100644 Platforms/AMD/Styx/Override/ArmPlatformPkg/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf -- 1.9.1

8 years, 7 months

[PATCH] Platforms/ARM/Juno: move to renamed PCI PCDs

by Ard Biesheuvel

Use the new PCI related PCD names after they have been moved from ArmPlatformPkg to ArmPkg Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel(a)linaro.org> --- Platforms/ARM/Juno/ArmJuno.dsc | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/Platforms/ARM/Juno/ArmJuno.dsc b/Platforms/ARM/Juno/ArmJuno.dsc index fbf09c220b8e..4f08e80d1483 100644 --- a/Platforms/ARM/Juno/ArmJuno.dsc +++ b/Platforms/ARM/Juno/ArmJuno.dsc @@ -140,13 +140,13 @@ # # PLDA PCI Root Complex # - gArmPlatformTokenSpaceGuid.PcdPciBusMax|255 - gArmPlatformTokenSpaceGuid.PcdPciIoBase|0x5f800000 - gArmPlatformTokenSpaceGuid.PcdPciIoSize|0x00800000 - gArmPlatformTokenSpaceGuid.PcdPciMmio32Base|0x50000000 - gArmPlatformTokenSpaceGuid.PcdPciMmio32Size|0x08000000 - gArmPlatformTokenSpaceGuid.PcdPciMmio64Base|0x4000000000 - gArmPlatformTokenSpaceGuid.PcdPciMmio64Size|0x100000000 + gArmTokenSpaceGuid.PcdPciBusMax|255 + gArmTokenSpaceGuid.PcdPciIoBase|0x5f800000 + gArmTokenSpaceGuid.PcdPciIoSize|0x00800000 + gArmTokenSpaceGuid.PcdPciMmio32Base|0x50000000 + gArmTokenSpaceGuid.PcdPciMmio32Size|0x08000000 + gArmTokenSpaceGuid.PcdPciMmio64Base|0x4000000000 + gArmTokenSpaceGuid.PcdPciMmio64Size|0x100000000 # List of Device Paths that support BootMonFs gArmPlatformTokenSpaceGuid.PcdBootMonFsSupportedDevicePaths|L"VenHw(E7223039-5836-41E1-B542-D7EC736C5E59)" -- 2.7.4

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Linaro-uefi April 2016