Linaro-uefi January 2018

linaro-uefi@lists.linaro.org

11 participants
12 discussions

[PATCH] platforms.config: hikey: Change default TOS_BIN

by Victor Chong

Now that most, if not all, Linaro builds have reverted to using upstream ATF instead of the 96boards-hikey fork, change the default TOS_BIN value to match. Signed-off-by: Victor Chong <victor.chong(a)linaro.org> --- platforms.config | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/platforms.config b/platforms.config index deb02f4..e47ba3b 100644 --- a/platforms.config +++ b/platforms.config @@ -194,9 +194,6 @@ PACKAGES_PATH=OpenPlatformPkg/Platforms/AMD/Styx/Binary UEFI_BIN=STYX_ROM.fd UEFI_IMAGE_DIR=Cello -# NOTE: If using upstream ATF, i.e. -# https://github.com/ARM-software/arm-trusted-firmware -# please set TOS_BIN=tee-pager.bin [hikey] LONGNAME=CircuitCo HiKey DSC=OpenPlatformPkg/Platforms/Hisilicon/HiKey/HiKey.dsc @@ -205,7 +202,7 @@ UEFI_BIN=BL33_AP_UEFI.fd UEFI_IMAGE_DIR=HiKey BUILD_ATF=yes ATF_SPD=opteed -TOS_BIN=tee.bin +TOS_BIN=tee-pager.bin TOS_PLATFORM_FLAVOR=hikey BUILD_TOS=yes SCP_BIN=OpenPlatformPkg/Platforms/Hisilicon/HiKey/Binary/mcuimage.bin -- 2.15.1

6 years, 1 month

[PATCH 0/2] Add support for ATF BL32_EXTRA1 and BL32_EXTRA2

by Victor Chong

Previously, we were using a 'headless' version of optee_os binary for hikey and hikey960. With BL32_EXTRA1 and BL32_EXTRA2, we now enable optee_os header parsing to allow dynamic runtime support of either a 64- or 32-bit optee_os builds, and also the pager feature. Victor Chong (2): atf, opteed: Support BL32_EXTRA1 and BL32_EXTRA2 platforms.config: hikey*: Set TOS_BIN_EXTRA{1,2} atf-build.sh | 14 ++++++++++++-- opteed-build.sh | 4 ++++ platforms.config | 10 ++++++++-- 3 files changed, 24 insertions(+), 4 deletions(-) -- 2.15.1

6 years, 1 month

[PATCH edk2-platforms v1 00/14] Improve D0x platforms and bug fix

by Ming Huang

MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit *** BLURB HERE *** Jason Zhang (4): Hisilicon/D05: Add PPTT support Hisilicon D03/D05: Add capsule upgrade support Hisilicon D03/D05: Open SasPlatform source code Hisilicon D03/D05: Open SnpPlatform source code Ming Huang (9): Hisilicon D03/D05：Switch to Generic BDS driver Hisilicon D03/D05: Optimize the feature of BMC set boot option Hisilicon/Smbios: modify type 4 Hisilicon/D05: Replace SP805Watchdog by WatchdogTimer driver. Hisilicon/D03: Replace SP805Watchdog by WatchdogTimer driver. Hisilicon/D05/ACPI: Add ITS PXM Hisilicon/D05/ACPI: Add Pcie, HNS and SAS PXM Hisilicon/Library: Add OsBootLib Hisilicon D03/D05: Update firmware version to 18.02 Yan Zhang (1): Hisilicon/PCIe: Disable PCIe ASPM Platform/Hisilicon/D03/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini | 45 ++ Platform/Hisilicon/D03/D03.dsc | 51 +- Platform/Hisilicon/D03/D03.fdf | 84 ++- Platform/Hisilicon/D05/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini | 45 ++ Platform/Hisilicon/D05/D05.dsc | 56 +- Platform/Hisilicon/D05/D05.fdf | 85 ++- Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.c | 89 +++ Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.h | 49 ++ Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.inf | 61 ++ Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c | 4 +- Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.c | 99 +++ Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.h | 43 ++ Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.inf | 60 ++ Silicon/Hisilicon/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc | 81 +++ Silicon/Hisilicon/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf | 50 ++ Silicon/Hisilicon/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c | 70 ++ Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 71 ++ Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h | 2 + Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc | 10 + Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl | 9 + Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 34 +- Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl | 19 +- Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h | 27 + Silicon/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc | 31 +- Silicon/Hisilicon/Hi1616/Pptt/Pptt.c | 447 +++++++++++++ Silicon/Hisilicon/Hi1616/Pptt/Pptt.h | 142 ++++ Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf | 55 ++ Silicon/Hisilicon/HisiPkg.dec | 3 + Silicon/Hisilicon/Hisilicon.dsc.inc | 12 +- Silicon/Hisilicon/Hisilicon.fdf.inc | 9 + Silicon/Hisilicon/Include/Library/AcpiNextLib.h | 10 +- Silicon/Hisilicon/Include/Library/BmcConfigBootLib.h | 31 + Silicon/Hisilicon/Include/Library/OemDevicePath.h | 54 ++ Silicon/Hisilicon/Include/Library/OsBootLib.h | 47 ++ Silicon/Hisilicon/Include/Protocol/PlatformSasProtocol.h | 11 + Silicon/Hisilicon/Include/Protocol/SnpPlatformProtocol.h | 32 + Silicon/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h | 2 + Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.c | 454 +++++++++++++ Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.inf | 51 ++ Silicon/Hisilicon/Library/OsBootLib/OsBoot.h | 124 ++++ Silicon/Hisilicon/Library/OsBootLib/OsBootLib.c | 217 +++++++ Silicon/Hisilicon/Library/OsBootLib/OsBootLib.inf | 59 ++ Silicon/Hisilicon/Library/OsBootLib/OsBootLibMisc.c | 514 +++++++++++++++ Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c | 601 +++++++++++++++++ Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.h | 59 ++ Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf | 91 +++ Silicon/Hisilicon/Library/PlatformBootManagerLib/QuietBoot.c | 681 ++++++++++++++++++++ Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.c | 106 +++ Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.inf | 51 ++ Silicon/Hisilicon/Library/PlatformIntelBdsLib/IntelBdsPlatform.c | 434 +------------ Silicon/Hisilicon/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf | 4 +- 51 files changed, 4987 insertions(+), 489 deletions(-) create mode 100644 Platform/Hisilicon/D03/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini create mode 100644 Platform/Hisilicon/D05/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini create mode 100644 Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.c create mode 100644 Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.h create mode 100644 Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.inf create mode 100644 Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.c create mode 100644 Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.h create mode 100644 Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.inf create mode 100644 Silicon/Hisilicon/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc create mode 100644 Silicon/Hisilicon/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf create mode 100644 Silicon/Hisilicon/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c create mode 100644 Silicon/Hisilicon/Hi1616/Pptt/Pptt.c create mode 100644 Silicon/Hisilicon/Hi1616/Pptt/Pptt.h create mode 100644 Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf create mode 100644 Silicon/Hisilicon/Include/Library/BmcConfigBootLib.h create mode 100644 Silicon/Hisilicon/Include/Library/OemDevicePath.h create mode 100644 Silicon/Hisilicon/Include/Library/OsBootLib.h create mode 100644 Silicon/Hisilicon/Include/Protocol/SnpPlatformProtocol.h create mode 100644 Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.c create mode 100644 Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.inf create mode 100644 Silicon/Hisilicon/Library/OsBootLib/OsBoot.h create mode 100644 Silicon/Hisilicon/Library/OsBootLib/OsBootLib.c create mode 100644 Silicon/Hisilicon/Library/OsBootLib/OsBootLib.inf create mode 100644 Silicon/Hisilicon/Library/OsBootLib/OsBootLibMisc.c create mode 100644 Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c create mode 100644 Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.h create mode 100644 Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf create mode 100644 Silicon/Hisilicon/Library/PlatformBootManagerLib/QuietBoot.c create mode 100644 Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.c create mode 100644 Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.inf -- 1.9.1

6 years, 1 month

[RFC] MdeModulePkg/PciHostBridgeDxe: Add support for address translation

by Heyi Guo

This is the draft patch for the discussion posted in edk2-devel mailing list: https://lists.01.org/pipermail/edk2-devel/2017-December/019289.html As discussed in the mailing list, we'd like to add support for PCI address translation which is necessary for some non-x86 platforms. I also want to minimize the changes to the generic host bridge driver and platform PciHostBridgeLib implemetations, so additional two interfaces are added to expose translation information of the platform. To be generic, I add translation for each type of IO or memory resources. The patch is still a RFC, so I only passed the build for qemu64 and the function has not been tested yet. Please let me know your comments about it. Thanks. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Heyi Guo <heyi.guo(a)linaro.org> Cc: Ruiyu Ni <ruiyu.ni(a)intel.com> Cc: Ard Biesheuvel <ard.biesheuvel(a)linaro.org> Cc: Star Zeng <star.zeng(a)intel.com> Cc: Eric Dong <eric.dong(a)intel.com> --- .../FdtPciHostBridgeLib/FdtPciHostBridgeLib.c | 19 ++++ .../Bus/Pci/PciHostBridgeDxe/PciHostBridge.c | 53 ++++++++--- .../Bus/Pci/PciHostBridgeDxe/PciRootBridge.h | 8 +- .../Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c | 101 ++++++++++++++++++--- MdeModulePkg/Include/Library/PciHostBridgeLib.h | 36 ++++++++ 5 files changed, 192 insertions(+), 25 deletions(-) diff --git a/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c b/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c index 5b9c887..0c8371a 100644 --- a/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c +++ b/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c @@ -360,6 +360,16 @@ PciHostBridgeGetRootBridges ( return &mRootBridge; } +PCI_ROOT_BRIDGE_TRANSLATION * +EFIAPI +PciHostBridgeGetTranslations ( + UINTN *Count + ) +{ + *Count = 0; + return NULL; +} + /** Free the root bridge instances array returned from PciHostBridgeGetRootBridges(). @@ -377,6 +387,15 @@ PciHostBridgeFreeRootBridges ( ASSERT (Count == 1); } +VOID +EFIAPI +PciHostBridgeFreeTranslations ( + PCI_ROOT_BRIDGE_TRANSLATION *Translations, + UINTN Count + ) +{ +} + /** Inform the platform that the resource conflict happens. diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c index 1494848..835e411 100644 --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c @@ -360,18 +360,38 @@ InitializePciHostBridge ( PCI_HOST_BRIDGE_INSTANCE *HostBridge; PCI_ROOT_BRIDGE_INSTANCE *RootBridge; PCI_ROOT_BRIDGE *RootBridges; + PCI_ROOT_BRIDGE_TRANSLATION *Translations; UINTN RootBridgeCount; + UINTN TranslationCount; UINTN Index; PCI_ROOT_BRIDGE_APERTURE *MemApertures[4]; + UINT64 MemTranslation[4]; UINTN MemApertureIndex; BOOLEAN ResourceAssigned; LIST_ENTRY *Link; + UINT64 Trans; RootBridges = PciHostBridgeGetRootBridges (&RootBridgeCount); if ((RootBridges == NULL) || (RootBridgeCount == 0)) { return EFI_UNSUPPORTED; } + Translations = PciHostBridgeGetTranslations (&TranslationCount); + if (Translations == NULL || TranslationCount == 0) { + TranslationCount = 0; + Translations = AllocateZeroPool (RootBridgeCount * sizeof (*Translations)); + if (Translations == NULL) { + PciHostBridgeFreeRootBridges (RootBridges, RootBridgeCount); + return EFI_OUT_OF_RESOURCES; + } + } + + if (TranslationCount != 0 && TranslationCount != RootBridgeCount) { + DEBUG ((DEBUG_ERROR, "Error: count of root bridges (%d) and translation (%d) are different!\n", + RootBridgeCount, TranslationCount)); + return EFI_INVALID_PARAMETER; + } + Status = gBS->LocateProtocol (&gEfiMetronomeArchProtocolGuid, NULL, (VOID **) &mMetronome); ASSERT_EFI_ERROR (Status); Status = gBS->LocateProtocol (&gEfiCpuIo2ProtocolGuid, NULL, (VOID **) &mCpuIo); @@ -395,7 +415,7 @@ InitializePciHostBridge ( // // Create Root Bridge Handle Instance // - RootBridge = CreateRootBridge (&RootBridges[Index]); + RootBridge = CreateRootBridge (&RootBridges[Index], &Translations[Index]); ASSERT (RootBridge != NULL); if (RootBridge == NULL) { continue; @@ -411,8 +431,9 @@ InitializePciHostBridge ( } if (RootBridges[Index].Io.Base <= RootBridges[Index].Io.Limit) { + Trans = Translations[Index].IoTranslation; Status = AddIoSpace ( - RootBridges[Index].Io.Base, + RootBridges[Index].Io.Base + Trans, RootBridges[Index].Io.Limit - RootBridges[Index].Io.Base + 1 ); ASSERT_EFI_ERROR (Status); @@ -422,7 +443,7 @@ InitializePciHostBridge ( EfiGcdIoTypeIo, 0, RootBridges[Index].Io.Limit - RootBridges[Index].Io.Base + 1, - &RootBridges[Index].Io.Base, + &RootBridges[Index].Io.Base + Trans, gImageHandle, NULL ); @@ -437,20 +458,24 @@ InitializePciHostBridge ( // the MEM aperture in Mem // MemApertures[0] = &RootBridges[Index].Mem; + MemTranslation[0] = Translations[Index].MemTranslation; MemApertures[1] = &RootBridges[Index].MemAbove4G; + MemTranslation[1] = Translations[Index].MemAbove4GTranslation; MemApertures[2] = &RootBridges[Index].PMem; + MemTranslation[2] = Translations[Index].PMemTranslation; MemApertures[3] = &RootBridges[Index].PMemAbove4G; + MemTranslation[3] = Translations[Index].PMemAbove4GTranslation; for (MemApertureIndex = 0; MemApertureIndex < ARRAY_SIZE (MemApertures); MemApertureIndex++) { if (MemApertures[MemApertureIndex]->Base <= MemApertures[MemApertureIndex]->Limit) { Status = AddMemoryMappedIoSpace ( - MemApertures[MemApertureIndex]->Base, + MemApertures[MemApertureIndex]->Base + MemTranslation[MemApertureIndex], MemApertures[MemApertureIndex]->Limit - MemApertures[MemApertureIndex]->Base + 1, EFI_MEMORY_UC ); ASSERT_EFI_ERROR (Status); Status = gDS->SetMemorySpaceAttributes ( - MemApertures[MemApertureIndex]->Base, + MemApertures[MemApertureIndex]->Base + MemTranslation[MemApertureIndex], MemApertures[MemApertureIndex]->Limit - MemApertures[MemApertureIndex]->Base + 1, EFI_MEMORY_UC ); @@ -463,7 +488,7 @@ InitializePciHostBridge ( EfiGcdMemoryTypeMemoryMappedIo, 0, MemApertures[MemApertureIndex]->Limit - MemApertures[MemApertureIndex]->Base + 1, - &MemApertures[MemApertureIndex]->Base, + &MemApertures[MemApertureIndex]->Base + MemTranslation[MemApertureIndex], gImageHandle, NULL ); @@ -514,7 +539,13 @@ InitializePciHostBridge ( ); ASSERT_EFI_ERROR (Status); } + PciHostBridgeFreeRootBridges (RootBridges, RootBridgeCount); + if (TranslationCount == 0) { + FreePool (Translations); + } else { + PciHostBridgeFreeTranslations (Translations, TranslationCount); + } if (!EFI_ERROR (Status)) { mIoMmuEvent = EfiCreateProtocolNotifyEvent ( @@ -828,7 +859,7 @@ NotifyPhase ( FALSE, RootBridge->ResAllocNode[Index].Length, MIN (15, BitsOfAlignment), - ALIGN_VALUE (RootBridge->Io.Base, Alignment + 1), + ALIGN_VALUE (RootBridge->Io.Base, Alignment + 1) + RootBridge->IoTranslation, RootBridge->Io.Limit ); break; @@ -838,7 +869,7 @@ NotifyPhase ( TRUE, RootBridge->ResAllocNode[Index].Length, MIN (63, BitsOfAlignment), - ALIGN_VALUE (RootBridge->MemAbove4G.Base, Alignment + 1), + ALIGN_VALUE (RootBridge->MemAbove4G.Base, Alignment + 1) + RootBridge->MemAbove4GTranslation, RootBridge->MemAbove4G.Limit ); if (BaseAddress != MAX_UINT64) { @@ -853,7 +884,7 @@ NotifyPhase ( TRUE, RootBridge->ResAllocNode[Index].Length, MIN (31, BitsOfAlignment), - ALIGN_VALUE (RootBridge->Mem.Base, Alignment + 1), + ALIGN_VALUE (RootBridge->Mem.Base, Alignment + 1) + RootBridge->MemTranslation, RootBridge->Mem.Limit ); break; @@ -863,7 +894,7 @@ NotifyPhase ( TRUE, RootBridge->ResAllocNode[Index].Length, MIN (63, BitsOfAlignment), - ALIGN_VALUE (RootBridge->PMemAbove4G.Base, Alignment + 1), + ALIGN_VALUE (RootBridge->PMemAbove4G.Base, Alignment + 1) + RootBridge->PMemAbove4GTranslation, RootBridge->PMemAbove4G.Limit ); if (BaseAddress != MAX_UINT64) { @@ -877,7 +908,7 @@ NotifyPhase ( TRUE, RootBridge->ResAllocNode[Index].Length, MIN (31, BitsOfAlignment), - ALIGN_VALUE (RootBridge->PMem.Base, Alignment + 1), + ALIGN_VALUE (RootBridge->PMem.Base, Alignment + 1) + RootBridge->PMemTranslation, RootBridge->PMem.Limit ); break; diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridge.h b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridge.h index d3dfb57..449c4b3 100644 --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridge.h +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridge.h @@ -73,6 +73,11 @@ typedef struct { PCI_ROOT_BRIDGE_APERTURE PMem; PCI_ROOT_BRIDGE_APERTURE MemAbove4G; PCI_ROOT_BRIDGE_APERTURE PMemAbove4G; + UINT64 IoTranslation; + UINT64 MemTranslation; + UINT64 MemAbove4GTranslation; + UINT64 PMemTranslation; + UINT64 PMemAbove4GTranslation; BOOLEAN DmaAbove4G; BOOLEAN NoExtendedConfigSpace; VOID *ConfigBuffer; @@ -98,7 +103,8 @@ typedef struct { **/ PCI_ROOT_BRIDGE_INSTANCE * CreateRootBridge ( - IN PCI_ROOT_BRIDGE *Bridge + IN PCI_ROOT_BRIDGE *Bridge, + IN PCI_ROOT_BRIDGE_TRANSLATION *Translation ); // diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c index dc06c16..84b2d5a 100644 --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c @@ -67,7 +67,8 @@ UINT8 mOutStride[] = { **/ PCI_ROOT_BRIDGE_INSTANCE * CreateRootBridge ( - IN PCI_ROOT_BRIDGE *Bridge + IN PCI_ROOT_BRIDGE *Bridge, + IN PCI_ROOT_BRIDGE_TRANSLATION *Translation ) { PCI_ROOT_BRIDGE_INSTANCE *RootBridge; @@ -87,11 +88,21 @@ CreateRootBridge ( (Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_MEM64_DECODE) != 0 ? L"Mem64Decode" : L"" )); DEBUG ((EFI_D_INFO, " Bus: %lx - %lx\n", Bridge->Bus.Base, Bridge->Bus.Limit)); - DEBUG ((EFI_D_INFO, " Io: %lx - %lx\n", Bridge->Io.Base, Bridge->Io.Limit)); - DEBUG ((EFI_D_INFO, " Mem: %lx - %lx\n", Bridge->Mem.Base, Bridge->Mem.Limit)); - DEBUG ((EFI_D_INFO, " MemAbove4G: %lx - %lx\n", Bridge->MemAbove4G.Base, Bridge->MemAbove4G.Limit)); - DEBUG ((EFI_D_INFO, " PMem: %lx - %lx\n", Bridge->PMem.Base, Bridge->PMem.Limit)); - DEBUG ((EFI_D_INFO, " PMemAbove4G: %lx - %lx\n", Bridge->PMemAbove4G.Base, Bridge->PMemAbove4G.Limit)); + DEBUG ((DEBUG_INFO, " Io: %lx - %lx translation=%lx\n", + Bridge->Io.Base, Bridge->Io.Limit, Translation->IoTranslation + )); + DEBUG ((DEBUG_INFO, " Mem: %lx - %lx translation=%lx\n", + Bridge->Mem.Base, Bridge->Mem.Limit, Translation->MemTranslation + )); + DEBUG ((DEBUG_INFO, " MemAbove4G: %lx - %lx translation=%lx\n", + Bridge->MemAbove4G.Base, Bridge->MemAbove4G.Limit, Translation->MemAbove4GTranslation + )); + DEBUG ((DEBUG_INFO, " PMem: %lx - %lx translation=%lx\n", + Bridge->PMem.Base, Bridge->PMem.Limit, Translation->PMemTranslation + )); + DEBUG ((DEBUG_INFO, " PMemAbove4G: %lx - %lx translation=%lx\n", + Bridge->PMemAbove4G.Base, Bridge->PMemAbove4G.Limit, Translation->PMemAbove4GTranslation + )); // // Make sure Mem and MemAbove4G apertures are valid @@ -174,10 +185,15 @@ CreateRootBridge ( CopyMem (&RootBridge->Bus, &Bridge->Bus, sizeof (PCI_ROOT_BRIDGE_APERTURE)); CopyMem (&RootBridge->Io, &Bridge->Io, sizeof (PCI_ROOT_BRIDGE_APERTURE)); + RootBridge->IoTranslation = Translation->IoTranslation; CopyMem (&RootBridge->Mem, &Bridge->Mem, sizeof (PCI_ROOT_BRIDGE_APERTURE)); + RootBridge->MemTranslation = Translation->MemTranslation; CopyMem (&RootBridge->MemAbove4G, &Bridge->MemAbove4G, sizeof (PCI_ROOT_BRIDGE_APERTURE)); + RootBridge->MemAbove4GTranslation = Translation->MemAbove4GTranslation; CopyMem (&RootBridge->PMem, &Bridge->PMem, sizeof (PCI_ROOT_BRIDGE_APERTURE)); + RootBridge->PMemTranslation = Translation->PMemTranslation; CopyMem (&RootBridge->PMemAbove4G, &Bridge->PMemAbove4G, sizeof (PCI_ROOT_BRIDGE_APERTURE)); + RootBridge->PMemAbove4GTranslation = Translation->PMemAbove4GTranslation; for (Index = TypeIo; Index < TypeMax; Index++) { switch (Index) { @@ -403,6 +419,28 @@ RootBridgeIoCheckParameter ( return EFI_SUCCESS; } +EFI_STATUS +RootBridgeIoGetMemTranslation ( + IN PCI_ROOT_BRIDGE_INSTANCE *RootBridge, + IN UINT64 Address, + IN OUT UINT64 *Translation + ) +{ + if (Address >= RootBridge->Mem.Base && Address <= RootBridge->Mem.Limit) { + *Translation = RootBridge->MemTranslation; + } else if (Address >= RootBridge->PMem.Base && Address <= RootBridge->PMem.Limit) { + *Translation = RootBridge->PMemTranslation; + } else if (Address >= RootBridge->MemAbove4G.Base && Address <= RootBridge->MemAbove4G.Limit) { + *Translation = RootBridge->MemAbove4GTranslation; + } else if (Address >= RootBridge->PMemAbove4G.Base && Address <= RootBridge->PMemAbove4G.Limit) { + *Translation = RootBridge->PMemAbove4GTranslation; + } else { + return EFI_INVALID_PARAMETER; + } + + return EFI_SUCCESS; +} + /** Polls an address in memory mapped I/O space until an exit condition is met, or a timeout occurs. @@ -658,13 +696,22 @@ RootBridgeIoMemRead ( ) { EFI_STATUS Status; + PCI_ROOT_BRIDGE_INSTANCE *RootBridge; + UINT64 Translation; Status = RootBridgeIoCheckParameter (This, MemOperation, Width, Address, Count, Buffer); if (EFI_ERROR (Status)) { return Status; } - return mCpuIo->Mem.Read (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width, Address, Count, Buffer); + + RootBridge = ROOT_BRIDGE_FROM_THIS (This); + Status = RootBridgeIoGetMemTranslation (RootBridge, Address, &Translation); + if (EFI_ERROR (Status)) { + return Status; + } + + return mCpuIo->Mem.Read (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width, Address + Translation, Count, Buffer); } /** @@ -705,13 +752,22 @@ RootBridgeIoMemWrite ( ) { EFI_STATUS Status; + PCI_ROOT_BRIDGE_INSTANCE *RootBridge; + UINT64 Translation; Status = RootBridgeIoCheckParameter (This, MemOperation, Width, Address, Count, Buffer); if (EFI_ERROR (Status)) { return Status; } - return mCpuIo->Mem.Write (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width, Address, Count, Buffer); + + RootBridge = ROOT_BRIDGE_FROM_THIS (This); + Status = RootBridgeIoGetMemTranslation (RootBridge, Address, &Translation); + if (EFI_ERROR (Status)) { + return Status; + } + + return mCpuIo->Mem.Write (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width, Address + Translation, Count, Buffer); } /** @@ -746,6 +802,8 @@ RootBridgeIoIoRead ( ) { EFI_STATUS Status; + PCI_ROOT_BRIDGE_INSTANCE *RootBridge; + Status = RootBridgeIoCheckParameter ( This, IoOperation, Width, Address, Count, Buffer @@ -753,7 +811,10 @@ RootBridgeIoIoRead ( if (EFI_ERROR (Status)) { return Status; } - return mCpuIo->Io.Read (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width, Address, Count, Buffer); + + RootBridge = ROOT_BRIDGE_FROM_THIS (This); + + return mCpuIo->Io.Read (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width, Address + RootBridge->IoTranslation, Count, Buffer); } /** @@ -788,6 +849,8 @@ RootBridgeIoIoWrite ( ) { EFI_STATUS Status; + PCI_ROOT_BRIDGE_INSTANCE *RootBridge; + Status = RootBridgeIoCheckParameter ( This, IoOperation, Width, Address, Count, Buffer @@ -795,7 +858,10 @@ RootBridgeIoIoWrite ( if (EFI_ERROR (Status)) { return Status; } - return mCpuIo->Io.Write (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width, Address, Count, Buffer); + + RootBridge = ROOT_BRIDGE_FROM_THIS (This); + + return mCpuIo->Io.Write (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width, Address + RootBridge->IoTranslation, Count, Buffer); } /** @@ -1621,19 +1687,28 @@ RootBridgeIoConfiguration ( switch (ResAllocNode->Type) { case TypeIo: - Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_IO; + Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_IO; + Descriptor->AddrTranslationOffset = RootBridge->IoTranslation; break; case TypePMem32: - Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE; + Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE; + Descriptor->AddrTranslationOffset = RootBridge->PMemTranslation; + Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM; + Descriptor->AddrSpaceGranularity = 32; case TypeMem32: + Descriptor->AddrTranslationOffset = RootBridge->MemTranslation; Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM; Descriptor->AddrSpaceGranularity = 32; break; case TypePMem64: - Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE; + Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE; + Descriptor->AddrTranslationOffset = RootBridge->PMemAbove4GTranslation; + Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM; + Descriptor->AddrSpaceGranularity = 64; case TypeMem64: + Descriptor->AddrTranslationOffset = RootBridge->MemAbove4GTranslation; Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM; Descriptor->AddrSpaceGranularity = 64; break; diff --git a/MdeModulePkg/Include/Library/PciHostBridgeLib.h b/MdeModulePkg/Include/Library/PciHostBridgeLib.h index d42e9ec..4c297fd 100644 --- a/MdeModulePkg/Include/Library/PciHostBridgeLib.h +++ b/MdeModulePkg/Include/Library/PciHostBridgeLib.h @@ -53,6 +53,14 @@ typedef struct { EFI_DEVICE_PATH_PROTOCOL *DevicePath; ///< Device path. } PCI_ROOT_BRIDGE; +typedef struct { + UINT64 IoTranslation; + UINT64 MemTranslation; + UINT64 MemAbove4GTranslation; + UINT64 PMemTranslation; + UINT64 PMemAbove4GTranslation; +} PCI_ROOT_BRIDGE_TRANSLATION; + /** Return all the root bridge instances in an array. @@ -69,6 +77,21 @@ PciHostBridgeGetRootBridges ( ); /** + Return all the root bridge instances in an array. + + @param Count Return the count of root bridge instances. + + @return All the root bridge instances in an array. + The array should be passed into PciHostBridgeFreeRootBridges() + when it's not used. +**/ +PCI_ROOT_BRIDGE_TRANSLATION * +EFIAPI +PciHostBridgeGetTranslations ( + UINTN *Count + ); + +/** Free the root bridge instances array returned from PciHostBridgeGetRootBridges(). @param Bridges The root bridge instances array. @@ -82,6 +105,19 @@ PciHostBridgeFreeRootBridges ( ); /** + Free the root bridge instances array returned from PciHostBridgeGetRootBridges(). + + @param Bridges The root bridge instances array. + @param Count The count of the array. +**/ +VOID +EFIAPI +PciHostBridgeFreeTranslations ( + PCI_ROOT_BRIDGE_TRANSLATION *Bridges, + UINTN Count + ); + +/** Inform the platform that the resource conflict happens. @param HostBridgeHandle Handle of the Host Bridge. -- 2.7.4

6 years, 2 months

[PATCH edk2-platforms v2 00/15] Improve D0x platforms and bug fix

by Ming Huang

The major features of this patchset include adding PPTT support, switching to Generic BDS driver, adding capsule upgrade support, open-source version for SnpPlatform and SasPlatform changing DmaLib to CoherentDmaLib(this one is omissive in v1). Code can also be found in github: https://github.com/hisilicon/OpenPlatformPkg.git branch: rp-1802-platforms-v2 Jason Zhang (3): Hisilicon D03/D05: Add capsule upgrade support Hisilicon D03/D05: Open SasPlatform source code Hisilicon D03/D05: Open SnpPlatform source code Ming Huang (11): Hisilicon/D05: Move Madt definition to head file Hisilicon/D05: Add PPTT support Hisilicon/D0x/BDS: Switch to Generic BDS driver Hisilicon/D0x: Break BMC SetBoot option out into separate library Hilisicon: Change DmaLib to CoherentDmaLib Hisilicon/Smbios: Indicate use of ProcessorFamily2 in type 4 table Hisilicon/D05: Replace SP805Watchdog by WatchdogTimer driver. Hisilicon/D03: Replace SP805Watchdog by WatchdogTimer driver. Hisilicon/D05/ACPI: Add ITS PXM Hisilicon/D05/ACPI: Add Pcie, HNS and SAS PXM Hisilicon D03/D05: Update firmware version to 18.02 Yan Zhang (1): Hisilicon/PCIe: Disable PCIe ASPM Platform/Hisilicon/D03/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini | 45 ++ Platform/Hisilicon/D03/D03.dsc | 42 +- Platform/Hisilicon/D03/D03.fdf | 79 ++- Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc | 81 +++ Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf | 50 ++ Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c | 70 +++ Platform/Hisilicon/D05/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini | 45 ++ Platform/Hisilicon/D05/D05.dsc | 47 +- Platform/Hisilicon/D05/D05.fdf | 80 ++- Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc | 81 +++ Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf | 50 ++ Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c | 70 +++ Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.c | 106 ++++ Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.inf | 45 ++ Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c | 4 +- Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.c | 115 ++++ Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.inf | 46 ++ Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.c | 2 +- Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.c | 3 +- Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 103 ++++ Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h | 2 + Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc | 10 + Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl | 9 + Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 34 +- Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl | 19 +- Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h | 30 +- Silicon/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc | 23 +- Silicon/Hisilicon/Hi1616/Pptt/Pptt.c | 540 ++++++++++++++++ Silicon/Hisilicon/Hi1616/Pptt/Pptt.h | 88 +++ Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf | 48 ++ Silicon/Hisilicon/HisiPkg.dec | 6 + Silicon/Hisilicon/Hisilicon.dsc.inc | 12 +- Silicon/Hisilicon/Hisilicon.fdf.inc | 9 + Silicon/Hisilicon/Include/Library/AcpiNextLib.h | 10 +- Silicon/Hisilicon/Include/Library/BmcConfigBootLib.h | 31 + Silicon/Hisilicon/Include/Library/OemDevicePath.h | 52 ++ Silicon/Hisilicon/Include/Protocol/HisiPlatformSasProtocol.h | 30 + Silicon/Hisilicon/Include/Protocol/SnpPlatformProtocol.h | 32 + Silicon/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h | 2 + Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.c | 466 ++++++++++++++ Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.inf | 51 ++ Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c | 643 ++++++++++++++++++++ Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.h | 31 + Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf | 74 +++ Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.c | 123 ++++ Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.inf | 51 ++ 46 files changed, 3536 insertions(+), 54 deletions(-) create mode 100644 Platform/Hisilicon/D03/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini create mode 100644 Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc create mode 100644 Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf create mode 100644 Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c create mode 100644 Platform/Hisilicon/D05/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini create mode 100644 Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc create mode 100644 Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf create mode 100644 Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c create mode 100644 Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.c create mode 100644 Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.inf create mode 100644 Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.c create mode 100644 Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.inf create mode 100644 Silicon/Hisilicon/Hi1616/Pptt/Pptt.c create mode 100644 Silicon/Hisilicon/Hi1616/Pptt/Pptt.h create mode 100644 Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf create mode 100644 Silicon/Hisilicon/Include/Library/BmcConfigBootLib.h create mode 100644 Silicon/Hisilicon/Include/Library/OemDevicePath.h create mode 100644 Silicon/Hisilicon/Include/Protocol/HisiPlatformSasProtocol.h create mode 100644 Silicon/Hisilicon/Include/Protocol/SnpPlatformProtocol.h create mode 100644 Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.c create mode 100644 Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.inf create mode 100644 Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c create mode 100644 Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.h create mode 100644 Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf create mode 100644 Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.c create mode 100644 Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.inf -- 1.9.1

6 years, 2 months

[PATCH edk2/MdePkg v1] Fix definition bug of Acpi62.h

by Heyi Guo

Correct processor struct of PPTT in Acpi62.h Ming Huang (1): MdePkg ACPI: Correct processor struct of PPTT MdePkg/Include/IndustryStandard/Acpi62.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 1.9.1

6 years, 2 months

[PATCH] atf-build: migrate to bl2_el3

by Haojian Zhuang

When migrate to BL2_EL3 in ARM Trusted Firmware, bl2.bin should be built out of fip.bin. Otherwise, non-TF ROM failes to load bl2.bin because it doesn't recognize fip.bin format. So copy bl2.bin to UEFI folder after ATF built. Signed-off-by: Haojian Zhuang <haojian.zhuang(a)linaro.org> --- atf-build.sh | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/atf-build.sh b/atf-build.sh index 65d4dbc..db741f5 100755 --- a/atf-build.sh +++ b/atf-build.sh @@ -182,9 +182,15 @@ function build_platform # Copy resulting images to UEFI image dir # if [ $VERBOSE -eq 1 ]; then - echo "Copying bl1.bin and fip.bin to "$WORKSPACE/Build/$PLATFORM_IMAGE_DIR/$BUILD_PROFILE/FV/"" + echo "Copying bl1.bin bl2.bin and fip.bin to "$WORKSPACE/Build/$PLATFORM_IMAGE_DIR/$BUILD_PROFILE/FV/"" fi - cp -a build/"$ATF_PLATFORM/$BUILD_TYPE"/{bl1,fip}.bin "$WORKSPACE/Build/$PLATFORM_IMAGE_DIR/$BUILD_PROFILE/FV/" + if [ -f build/"$ATF_PLATFORM/$BUILD_TYPE"/bl1.bin ]; then + cp -a build/"$ATF_PLATFORM/$BUILD_TYPE"/bl1.bin "$WORKSPACE/Build/$PLATFORM_IMAGE_DIR/$BUILD_PROFILE/FV/" + fi + if [ -f build/"$ATF_PLATFORM/$BUILD_TYPE"/bl2.bin ]; then + cp -a build/"$ATF_PLATFORM/$BUILD_TYPE"/bl2.bin "$WORKSPACE/Build/$PLATFORM_IMAGE_DIR/$BUILD_PROFILE/FV/" + fi + cp -a build/"$ATF_PLATFORM/$BUILD_TYPE"/fip.bin "$WORKSPACE/Build/$PLATFORM_IMAGE_DIR/$BUILD_PROFILE/FV/" else return 1 fi -- 2.7.4

6 years, 2 months

[PATCH edk2/MdePkg v1] Fix definiton bug of Acpi62.h

by Heyi Guo

From: Ming Huang <huangming23(a)huawei.com> Correct processor flags struct of PPTT in Acpi62.h. Ming Huang (1): MdePkg ACPI: Correct processor flags struct of PPTT MdePkg/Include/IndustryStandard/Acpi62.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 1.9.1

6 years, 2 months

[PATCH edk2-non-osi v2 0/7] Improve D0x platforms and bug fix

by Heyi Guo

The major features of this patchset: 1 Upgrade trusted firmware to 1.4 2 Workarounds for CVE-2017-5715 on Cortex A57/A72/A73 and A75 #1214 3 Delete some binary for open-source version 4 Update binary follow changing DmaLib to CoherentDmaLib Code can also be found in github: https://github.com/hisilicon/OpenPlatformPkg.git branch: rp-1802-osi-v2 Heyi Guo (6): Hisilicon D0x: Fix network interface order issue Hisilicon D0x: Delete SnpPlatform Hisilicon D03/D05: Update SasDriverDxe binary Hisilicon D03/D05: Update NativeOhci binary Hisilicon/D03: Update binary of trusted-firmware Hisilicon/D05: Update binary of trusted-firmware Jason Zhang (1): Hisilicon D03/D05: Delete SasPlatform Platform/Hisilicon/D03/Drivers/Net/SnpPV600Dxe/SnpPV600Dxe.efi | Bin 26688 -> 27392 bytes Platform/Hisilicon/D03/Drivers/Net/SnpPlatform/SnpPlatform.efi | Bin 3040 -> 0 bytes Platform/Hisilicon/D03/Drivers/Net/SnpPlatform/SnpPlatform.inf | 24 -------------------- Platform/Hisilicon/D03/Drivers/OhciDxe/NativeOhci.efi | Bin 21664 -> 22336 bytes Platform/Hisilicon/D03/Drivers/Sas/SasDriverDxe.efi | Bin 98112 -> 100224 bytes Platform/Hisilicon/D03/Drivers/SasPlatform/SasPlatform.efi | Bin 3040 -> 0 bytes Platform/Hisilicon/D03/Drivers/SasPlatform/SasPlatform.inf | 24 -------------------- Platform/Hisilicon/D03/bl1.bin | Bin 14336 -> 12416 bytes Platform/Hisilicon/D03/fip.bin | Bin 62513 -> 66758 bytes Platform/Hisilicon/D05/Drivers/Net/SnpPV600Dxe/SnpPV600Dxe.efi | Bin 28544 -> 27680 bytes Platform/Hisilicon/D05/Drivers/Net/SnpPlatform/SnpPlatform.efi | Bin 3392 -> 0 bytes Platform/Hisilicon/D05/Drivers/Net/SnpPlatform/SnpPlatform.inf | 24 -------------------- Platform/Hisilicon/D05/Drivers/OhciDxe/NativeOhci.efi | Bin 23328 -> 22624 bytes Platform/Hisilicon/D05/Drivers/Sas/SasDriverDxe.efi | Bin 112832 -> 115008 bytes Platform/Hisilicon/D05/Drivers/SasPlatform/SasPlatform.efi | Bin 3424 -> 0 bytes Platform/Hisilicon/D05/Drivers/SasPlatform/SasPlatform.inf | 24 -------------------- Platform/Hisilicon/D05/bl1.bin | Bin 14344 -> 12424 bytes Platform/Hisilicon/D05/fip.bin | Bin 41493 -> 37546 bytes 18 files changed, 96 deletions(-) delete mode 100644 Platform/Hisilicon/D03/Drivers/Net/SnpPlatform/SnpPlatform.efi delete mode 100644 Platform/Hisilicon/D03/Drivers/Net/SnpPlatform/SnpPlatform.inf delete mode 100644 Platform/Hisilicon/D03/Drivers/SasPlatform/SasPlatform.efi delete mode 100644 Platform/Hisilicon/D03/Drivers/SasPlatform/SasPlatform.inf delete mode 100644 Platform/Hisilicon/D05/Drivers/Net/SnpPlatform/SnpPlatform.efi delete mode 100644 Platform/Hisilicon/D05/Drivers/Net/SnpPlatform/SnpPlatform.inf delete mode 100644 Platform/Hisilicon/D05/Drivers/SasPlatform/SasPlatform.efi delete mode 100644 Platform/Hisilicon/D05/Drivers/SasPlatform/SasPlatform.inf -- 1.9.1

6 years, 2 months

[PATCH edk2-non-osi v1 0/2] Update binary of trusted-firmware

by Heyi Guo

Workarounds for CVE-2017-5715 on Cortex A57/A72/A73 and A75 #1214. Heyi Guo (2): Hisilicon/D03: Update binary of trusted-firmware Hisilicon/D05: Update binary of trusted-firmware Platform/Hisilicon/D03/bl1.bin | Bin 14336 -> 12416 bytes Platform/Hisilicon/D03/fip.bin | Bin 62513 -> 66758 bytes Platform/Hisilicon/D05/bl1.bin | Bin 14344 -> 12424 bytes Platform/Hisilicon/D05/fip.bin | Bin 41493 -> 37546 bytes 4 files changed, 0 insertions(+), 0 deletions(-) -- 1.9.1

6 years, 3 months

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Linaro-uefi January 2018