Linaro-uefi August 2016

linaro-uefi@lists.linaro.org

15 participants
26 discussions

[PATCH v2] Platforms/ARM: fix gtdt.asl for VExpressPkg

by fu.wei＠linaro.org

From: Fu Wei <fu.wei(a)linaro.org> Add Memory-mapped GT and SBSA Generic Watchdog timer info base on Foundation Model. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Fu Wei <fu.wei(a)linaro.org> --- Changelog: v2: Fix a inappropriate definition: GTDT_TIMER_SECURE --> GTDT_TIMER_SAVE_CONTEXT v1: The first upstreaming version: https://lists.linaro.org/pipermail/linaro-uefi/2016-July/002230.html Platforms/ARM/VExpress/AcpiTables/Gtdt.aslc | 128 ++++++++++++++++++++++------ 1 file changed, 101 insertions(+), 27 deletions(-) diff --git a/Platforms/ARM/VExpress/AcpiTables/Gtdt.aslc b/Platforms/ARM/VExpress/AcpiTables/Gtdt.aslc index 142249f..fc8f91f 100644 --- a/Platforms/ARM/VExpress/AcpiTables/Gtdt.aslc +++ b/Platforms/ARM/VExpress/AcpiTables/Gtdt.aslc @@ -19,21 +19,70 @@ #include <Library/PcdLib.h> #include <IndustryStandard/Acpi61.h> -#define SECURE_TIMER_EL1_GSIV 0x1D -#define NON_SECURE_TIMER_EL1_GSIV 0x1E -#define VIRTUAL_TIMER_GSIV 0x1B -#define NON_SECURE_EL2_GSIV 0x1A +#define FVP_SYSTEM_TIMER_BASE_ADDRESS 0x000000002a430000 +#define FVP_CNT_READ_BASE_ADDRESS 0x000000002a800000 -#define GT_BLOCK_CTL_BASE 0x000000002A810000 -#define GT_BLOCK_FRAME1_CTL_BASE 0x000000002A820000 -#define GT_BLOCK_FRAME1_GSIV 0x29 +#define FVP_SECURE_TIMER_EL1_GSIV 0x1D +#define FVP_NON_SECURE_TIMER_EL1_GSIV 0x1E +#define FVP_VIRTUAL_TIMER_GSIV 0x1B +#define FVP_NON_SECURE_EL2_GSIV 0x1A + +#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE +#define GTDT_TIMER_LEVEL_TRIGGERED 0 +#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY +#define GTDT_TIMER_ACTIVE_HIGH 0 +#define GTDT_TIMER_SAVE_CONTEXT EFI_ACPI_6_1_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY +#define GTDT_TIMER_LOSE_CONTEXT 0 + +#define FVP_GTDT_GTIMER_FLAGS (GTDT_TIMER_LOSE_CONTEXT | GTDT_TIMER_ACTIVE_HIGH | GTDT_TIMER_EDGE_TRIGGERED) + +#define FVP_PLATFORM_TIMER_COUNT 2 +#define FVP_TIMER_FRAMES_COUNT 2 +#define FVP_WATCHDOG_COUNT 1 + +#define FVP_GT_BLOCK_CTL_BASE 0x000000002A810000 +#define FVP_GT_BLOCK_FRAME0_CTL_BASE 0x000000002A820000 +#define FVP_GT_BLOCK_FRAME0_CTL_EL0_BASE 0xFFFFFFFFFFFFFFFF +#define FVP_GT_BLOCK_FRAME0_GSIV 0x39 + +#define FVP_GT_BLOCK_FRAME1_CTL_BASE 0x000000002A830000 +#define FVP_GT_BLOCK_FRAME1_CTL_EL0_BASE 0xFFFFFFFFFFFFFFFF +#define FVP_GT_BLOCK_FRAME1_GSIV 0x3A + +#define GTX_TIMER_EDGE_TRIGGERED EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE +#define GTX_TIMER_LEVEL_TRIGGERED 0 +#define GTX_TIMER_ACTIVE_LOW EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY +#define GTX_TIMER_ACTIVE_HIGH 0 + +#define FVP_GTX_TIMER_FLAGS (GTX_TIMER_ACTIVE_HIGH | GTX_TIMER_LEVEL_TRIGGERED) + +#define GTX_TIMER_SECURE EFI_ACPI_6_1_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER +#define GTX_TIMER_NON_SECURE 0 +#define GTX_TIMER_SAVE_CONTEXT EFI_ACPI_6_1_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY +#define GTX_TIMER_LOSE_CONTEXT 0 + +#define FVP_GTX_COMMON_FLAGS (GTX_TIMER_SAVE_CONTEXT | GTX_TIMER_SECURE) + +#define FVP_SBSA_WATCHDOG_REFRESH_BASE 0x000000002a450000 +#define FVP_SBSA_WATCHDOG_CONTROL_BASE 0x000000002a440000 +#define FVP_SBSA_WATCHDOG_GSIV 0x3B + +#define SBSA_WATCHDOG_EDGE_TRIGGERED EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE +#define SBSA_WATCHDOG_LEVEL_TRIGGERED 0 +#define SBSA_WATCHDOG_ACTIVE_LOW EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY +#define SBSA_WATCHDOG_ACTIVE_HIGH 0 +#define SBSA_WATCHDOG_SECURE EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER +#define SBSA_WATCHDOG_NON_SECURE 0 + +#define FVP_SBSA_WATCHDOG_FLAGS (SBSA_WATCHDOG_NON_SECURE | SBSA_WATCHDOG_ACTIVE_HIGH | SBSA_WATCHDOG_LEVEL_TRIGGERED) #pragma pack (1) typedef struct { EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt; EFI_ACPI_6_1_GTDT_GT_BLOCK_STRUCTURE GtBlock; - EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_STRUCTURE Frames[1]; + EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_STRUCTURE Frames[FVP_TIMER_FRAMES_COUNT]; + EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdogs[FVP_WATCHDOG_COUNT]; } FVP_GENERIC_TIMER_DESCRIPTION_TABLES; #pragma pack () @@ -45,27 +94,28 @@ FVP_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = { FVP_GENERIC_TIMER_DESCRIPTION_TABLES, EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION ), - 0xFFFFFFFFFFFFFFFF, // UINT64 PhysicalAddress + FVP_SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress EFI_ACPI_RESERVED_DWORD, // UINT32 Reserved - SECURE_TIMER_EL1_GSIV, // UINT32 SecurePL1TimerGSIV - EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE, // UINT32 SecurePL1TimerFlags - NON_SECURE_TIMER_EL1_GSIV, // UINT32 NonSecurePL1TimerGSIV - EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE, // UINT32 NonSecurePL1TimerFlags - VIRTUAL_TIMER_GSIV, // UINT32 VirtualTimerGSIV - EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE, // UINT32 VirtualTimerFlags - NON_SECURE_EL2_GSIV, // UINT32 NonSecurePL2TimerGSIV - EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE, // UINT32 NonSecurePL2TimerFlags - 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBasePhysicalAddress - 1, // UINT32 PlatformTimerCount + FVP_SECURE_TIMER_EL1_GSIV, // UINT32 SecurePL1TimerGSIV + FVP_GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags + FVP_NON_SECURE_TIMER_EL1_GSIV, // UINT32 NonSecurePL1TimerGSIV + FVP_GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags + FVP_VIRTUAL_TIMER_GSIV, // UINT32 VirtualTimerGSIV + FVP_GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags + FVP_NON_SECURE_EL2_GSIV, // UINT32 NonSecurePL2TimerGSIV + FVP_GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL2TimerFlags + FVP_CNT_READ_BASE_ADDRESS, // UINT64 CntReadBasePhysicalAddress + FVP_PLATFORM_TIMER_COUNT, // UINT32 PlatformTimerCount sizeof (EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset }, { EFI_ACPI_6_1_GTDT_GT_BLOCK, // UINT8 Type sizeof(EFI_ACPI_6_1_GTDT_GT_BLOCK_STRUCTURE) // UINT16 Length - + sizeof(EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_STRUCTURE), + + sizeof(EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_STRUCTURE) * + FVP_TIMER_FRAMES_COUNT, EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved - GT_BLOCK_CTL_BASE, // UINT64 CntCtlBase - 1, // UINT32 GTBlockTimerCount + FVP_GT_BLOCK_CTL_BASE, // UINT64 CntCtlBase + FVP_TIMER_FRAMES_COUNT, // UINT32 GTBlockTimerCount sizeof(EFI_ACPI_6_1_GTDT_GT_BLOCK_STRUCTURE) // UINT32 GTBlockTimerOffset }, { @@ -74,13 +124,37 @@ FVP_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = { {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE}, // UINT8 Reserved[3] - GT_BLOCK_FRAME1_CTL_BASE, // UINT64 CntBaseX - 0xFFFFFFFFFFFFFFFF, // UINT64 CntEL0BaseX - GT_BLOCK_FRAME1_GSIV, // UINT32 GTxPhysicalTimerGSIV - 0, // UINT32 GTxPhysicalTimerFlags + FVP_GT_BLOCK_FRAME0_CTL_BASE, // UINT64 CntBaseX + FVP_GT_BLOCK_FRAME0_CTL_EL0_BASE, // UINT64 CntEL0BaseX + FVP_GT_BLOCK_FRAME0_GSIV, // UINT32 GTxPhysicalTimerGSIV + FVP_GTX_TIMER_FLAGS, // UINT32 GTxPhysicalTimerFlags 0, // UINT32 GTxVirtualTimerGSIV 0, // UINT32 GTxVirtualTimerFlags - 0 // UINT32 GTxCommonFlags + FVP_GTX_COMMON_FLAGS // UINT32 GTxCommonFlags + }, + { + 1, // UINT8 GTFrameNumber + {EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE}, // UINT8 Reserved[3] + FVP_GT_BLOCK_FRAME1_CTL_BASE, // UINT64 CntBaseX + FVP_GT_BLOCK_FRAME1_CTL_EL0_BASE, // UINT64 CntEL0BaseX + FVP_GT_BLOCK_FRAME1_GSIV, // UINT32 GTxPhysicalTimerGSIV + FVP_GTX_TIMER_FLAGS, // UINT32 GTxPhysicalTimerFlags + 0, // UINT32 GTxVirtualTimerGSIV + 0, // UINT32 GTxVirtualTimerFlags + FVP_GTX_COMMON_FLAGS // UINT32 GTxCommonFlags + } + }, + { + { + EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG, // UINT8 Type + sizeof(EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE), // UINT16 Length + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved + FVP_SBSA_WATCHDOG_REFRESH_BASE, // UINT64 RefreshFramePhysicalAddress + FVP_SBSA_WATCHDOG_CONTROL_BASE, // UINT64 WatchdogControlFramePhysicalAddress + FVP_SBSA_WATCHDOG_GSIV, // UINT32 WatchdogTimerGSIV + FVP_SBSA_WATCHDOG_FLAGS // UINT32 WatchdogTimerFlags } } }; -- 2.5.5

7 years, 2 months

[PATCH v6 00/23] Marvell Armada7040 SoC support

by Marcin Wojtas

Hello, Here's 6th version of the support. It's rebased on top of newest master branch and comprise fixes from the latest review. Patches are also available in the github: https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits/opp… Any comments or remarks would be welcome. Best regards, Marcin Changelog: v5 -> v6 * Initial support - Enable compilation after ArmMmuLib was added to edk2 - Remove commented-out line - Enable up to 64MB RamDisk space for all Armada platforms - Move adding "-fno-unwind-tables" build flag to a separate patch and add explanation for this change * I2C - Change MvI2cDevicePathProtocol to STATIC in MvI2cDxe.c - Generate new I2C_GUID - Move I2C_GUID to header files and extend existing FIXME comment * Fupdate - Add FIXME note over including relative path from edk2. It was needed after fixing regression by replacing ShellExecute with RunShellCommand v4 -> v5 * Add ParsePcdLib - Library created in order to parse PCD strings - it makes support for multi-controller easier to implement * I2c - Introduce multi-bus support - Remove comments regarding GUID-slave address dependency - Add FIXME comment about no-restart dual definition * eeprom command - Enable selecting I2C bus - Add FIXME comment about no-restart dual definition * Spi - Fix writing procedure - Rename protocol to MARVELL_SPI_MASTER_PROTOCOL * General - Remove commented-out, unused lines v3 -> v4 * Update license messages - Unify - Add "Based on" statement were needed - Wrap every message at 80 characters - Add Marvell copyrights * Fix namings - All protocol/file names updated as suggested in review * Clean-up - Remove unneded blank lines and spaces - Fix typos * Add "Reviewed by" for currently accepted patches * Add support for new platform - Armada70x0 - Remove support for old platforms Apn806 and Armada7040_rz - Armada70x0 is based on Armada7040_rz with silicone fixes and improvements - No changes on drivers/libraries caused by this change - Update commit logs in whole tree * MppLib - Fix issue with writing to uninitialized memory * I2c and eeprom command - Remove dependency on BdsLibConnectAll call - I2c stack is connected only if eeprom command is executed and only in case it wasn't done before - gBS->ConnectController() used * BdsLib - Remove import of BdsLib - After rebase on top of new edk2, extra BdsLibConnectAll call isn't necessary (actually for now no BdsLibConnectAll is needed at all for our platform support) * sf command - Remove inclusion of relative path - Necessary macro now defined in globally exported file * RamDisk driver - Drop patch with this feature - As long as there is no possibility to format RamDisk with FAT, driver is not useful on Armada70x0 * fupdate command - Fix issue with "bad checksum" v2 -> v3 * Decrease binary size * Fupdate command - Remove regression - replace ShellExecute with RunShellCommand - Improve error paths * Add proper DEBUG library and change error print levels v1 -> v2 * Fix "may be used uninitialized" variables issue, branch compiles both with DEBUG and RELEASE flags * Remove I2C_FLAG_NORESTART dependency - replace it with local definition * Remove Marvell UART Library: - DW8250 IP has programming interface compatible with NS-16550. Since in edk2 there is support for 16550, internal library is unnecessary. - /Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf is used instead * RamDisk driver: - Remove old driver imported from EFI TOOLKIT 2.0 - Replace it with new MdeModulePkg/Universal/Disk/RamDiskDxe from edk2 - Lack of FAT formatting issue emerged * Add explicit dependency on IoLib in Drivers/Spi/SpiDxe.inf * Add poster's "Signed-off-by" registry to every commit message * Move to 05.04.2016 HEAD of edk2/master - Update CpuExceptionHandlerLib within OPP. Bartosz Szczepanek (3): Drivers/I2c: Create MvI2cDxe driver Drivers/I2c: Add MvEeprom driver Aplications/Eeprom: Add 'eeprom' command to shell Haim Boot (1): Platforms/Marvell: Enable compilation with aarch64-linux-gnueabi toolchain Jan Dąbroś (17): Platforms/Marvell: Create MppLib Platforms/Marvell: Armada: Enable MppLib on Armada70x0 platform Platforms/Marvell: Create ParsePcdLib Platforms/Marvell: Enable ParsePcdLib for Armada70x0 platform Platforms/Marvell: Enable I2C driver on Armada70x0 platform Plaforms/Marvell: Enable EEPROM driver on Armada70x0 platform Platforms/Marvell: Enable 'eeprom' command on Armada70x0 platform Platforms/Marvell: Add MARVELL_SPI_MASTER_PROTOCOL Drivers/Spi: Add Spi master driver Platforms/Marvell: Enable Spi master driver for Armada70x0 platform Platforms/Marvell: Add MARVELL_SPI_FLASH_PROTOCOL Drivers/Spi: Implement Spi flash driver Platforms/Marvell: Enable Spi flash driver for Armada70x0 platform Applications/SpiTool: Add 'sf' command utility Platforms/Marvell: Enable 'sf' command on Armada70x0 platform Applications/FirmwareUpdate: Add 'fupdate' comand to shell Platforms/Marvell: Enable 'fupdate' command on Armada70x0 platform Yehuda Yitschak (2): Platforms/Marvell: Add initial support for Armada70x0 SOC lib Platforms/Marvell: Add support for Armada70x0 platform Applications/EepromCmd/EepromCmd.c | 397 +++++++++++ Applications/EepromCmd/EepromCmd.inf | 71 ++ Applications/EepromCmd/EepromCmd.uni | Bin 0 -> 6816 bytes Applications/FirmwareUpdate/FUpdate.c | 448 +++++++++++++ Applications/FirmwareUpdate/FUpdate.inf | 68 ++ Applications/FirmwareUpdate/FUpdate.uni | Bin 0 -> 5838 bytes Applications/SpiTool/SpiFlashCmd.c | 526 +++++++++++++++ Applications/SpiTool/SpiFlashCmd.inf | 75 +++ Applications/SpiTool/SpiFlashCmd.uni | Bin 0 -> 7216 bytes Documentation/Marvell/Drivers/EepromDriver.txt | 96 +++ Documentation/Marvell/Drivers/I2cDriver.txt | 64 ++ Documentation/Marvell/Drivers/SpiDriver.txt | 116 ++++ Documentation/Marvell/PortingGuide/I2c.txt | 20 + Documentation/Marvell/PortingGuide/Mpp.txt | 48 ++ Documentation/Marvell/PortingGuide/Spi.txt | 15 + Documentation/Marvell/PortingGuide/SpiFlash.txt | 23 + Drivers/I2c/Devices/MvEeprom/MvEeprom.c | 292 ++++++++ Drivers/I2c/Devices/MvEeprom/MvEeprom.h | 103 +++ Drivers/I2c/Devices/MvEeprom/MvEeprom.inf | 70 ++ Drivers/I2c/MvI2cDxe/MvI2cDxe.c | 739 +++++++++++++++++++++ Drivers/I2c/MvI2cDxe/MvI2cDxe.h | 269 ++++++++ Drivers/I2c/MvI2cDxe/MvI2cDxe.inf | 75 +++ Drivers/Spi/Devices/MvSpiFlash.c | 531 +++++++++++++++ Drivers/Spi/Devices/MvSpiFlash.h | 132 ++++ Drivers/Spi/Devices/MvSpiFlash.inf | 67 ++ Drivers/Spi/MvSpiDxe.c | 379 +++++++++++ Drivers/Spi/MvSpiDxe.h | 145 ++++ Drivers/Spi/MvSpiDxe.inf | 66 ++ Platforms/Marvell/Armada/Armada.dsc.inc | 453 +++++++++++++ Platforms/Marvell/Armada/Armada70x0.dsc | 97 +++ Platforms/Marvell/Armada/Armada70x0.fdf | 270 ++++++++ .../Armada70x0Lib/AArch64/ArmPlatformHelper.S | 66 ++ .../Armada/Library/Armada70x0Lib/Armada70x0Lib.c | 155 +++++ .../Armada/Library/Armada70x0Lib/Armada70x0Lib.inf | 69 ++ .../Library/Armada70x0Lib/Armada70x0LibMem.c | 93 +++ Platforms/Marvell/Include/Library/MppLib.h | 42 ++ Platforms/Marvell/Include/Library/ParsePcdLib.h | 46 ++ Platforms/Marvell/Include/Protocol/Eeprom.h | 60 ++ Platforms/Marvell/Include/Protocol/Spi.h | 105 +++ Platforms/Marvell/Include/Protocol/SpiFlash.h | 113 ++++ Platforms/Marvell/Library/MppLib/MppLib.c | 163 +++++ Platforms/Marvell/Library/MppLib/MppLib.inf | 107 +++ .../Marvell/Library/ParsePcdLib/ParsePcdLib.c | 228 +++++++ .../Marvell/Library/ParsePcdLib/ParsePcdLib.inf | 50 ++ Platforms/Marvell/Marvell.dec | 136 ++++ 45 files changed, 7088 insertions(+) create mode 100644 Applications/EepromCmd/EepromCmd.c create mode 100644 Applications/EepromCmd/EepromCmd.inf create mode 100644 Applications/EepromCmd/EepromCmd.uni create mode 100644 Applications/FirmwareUpdate/FUpdate.c create mode 100644 Applications/FirmwareUpdate/FUpdate.inf create mode 100644 Applications/FirmwareUpdate/FUpdate.uni create mode 100644 Applications/SpiTool/SpiFlashCmd.c create mode 100644 Applications/SpiTool/SpiFlashCmd.inf create mode 100644 Applications/SpiTool/SpiFlashCmd.uni create mode 100644 Documentation/Marvell/Drivers/EepromDriver.txt create mode 100644 Documentation/Marvell/Drivers/I2cDriver.txt create mode 100644 Documentation/Marvell/Drivers/SpiDriver.txt create mode 100644 Documentation/Marvell/PortingGuide/I2c.txt create mode 100644 Documentation/Marvell/PortingGuide/Mpp.txt create mode 100644 Documentation/Marvell/PortingGuide/Spi.txt create mode 100644 Documentation/Marvell/PortingGuide/SpiFlash.txt create mode 100644 Drivers/I2c/Devices/MvEeprom/MvEeprom.c create mode 100644 Drivers/I2c/Devices/MvEeprom/MvEeprom.h create mode 100644 Drivers/I2c/Devices/MvEeprom/MvEeprom.inf create mode 100755 Drivers/I2c/MvI2cDxe/MvI2cDxe.c create mode 100644 Drivers/I2c/MvI2cDxe/MvI2cDxe.h create mode 100755 Drivers/I2c/MvI2cDxe/MvI2cDxe.inf create mode 100755 Drivers/Spi/Devices/MvSpiFlash.c create mode 100755 Drivers/Spi/Devices/MvSpiFlash.h create mode 100644 Drivers/Spi/Devices/MvSpiFlash.inf create mode 100755 Drivers/Spi/MvSpiDxe.c create mode 100644 Drivers/Spi/MvSpiDxe.h create mode 100644 Drivers/Spi/MvSpiDxe.inf create mode 100644 Platforms/Marvell/Armada/Armada.dsc.inc create mode 100644 Platforms/Marvell/Armada/Armada70x0.dsc create mode 100644 Platforms/Marvell/Armada/Armada70x0.fdf create mode 100644 Platforms/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelper.S create mode 100644 Platforms/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.c create mode 100644 Platforms/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf create mode 100644 Platforms/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c create mode 100644 Platforms/Marvell/Include/Library/MppLib.h create mode 100644 Platforms/Marvell/Include/Library/ParsePcdLib.h create mode 100644 Platforms/Marvell/Include/Protocol/Eeprom.h create mode 100644 Platforms/Marvell/Include/Protocol/Spi.h create mode 100644 Platforms/Marvell/Include/Protocol/SpiFlash.h create mode 100644 Platforms/Marvell/Library/MppLib/MppLib.c create mode 100644 Platforms/Marvell/Library/MppLib/MppLib.inf create mode 100644 Platforms/Marvell/Library/ParsePcdLib/ParsePcdLib.c create mode 100644 Platforms/Marvell/Library/ParsePcdLib/ParsePcdLib.inf create mode 100644 Platforms/Marvell/Marvell.dec -- 1.8.3.1

7 years, 5 months

[PATCH v6 0/4] arm64, xen: add xen_boot support into grup-mkconfig

by fu.wei＠linaro.org

From: Fu Wei <fu.wei(a)linaro.org> This patchset add xen_boot support into grup-mkconfig for generating xen boot entrances automatically Also update the docs/grub.texi for new xen_boot commands. This patchset has been tested on Foudation model with a bug fix: http://lists.gnu.org/archive/html/grub-devel/2016-02/msg00205.html ChangeLog: v6: http://lists.gnu.org/archive/html/grub-devel/2016-07/ Fix Coding style of util/grub.d/20_linux_xen.in, use soft tab. v5: http://lists.gnu.org/archive/html/grub-devel/2016-07/msg00008.html Update the introduction of xen_module commands in docs/grub.texi, according to the suggestion from Julien Grall v4: http://lists.gnu.org/archive/html/grub-devel/2016-05/ according to the XSM loading mechanism of Xen(upstreamed), update the introduction of xen_module commands in docs/grub.texi v3: http://lists.gnu.org/archive/html/grub-devel/2016-02/msg00314.html reorder the patches update the introduction of xen_module commands in docs/grub.texi v2: http://lists.gnu.org/archive/html/grub-devel/2016-02/msg00282.html add "--nounzip" option support in xen_module use "feature_xen_boot" instead of "grub_xen_boot" update the introduction of xen boot commands in docs/grub.texi v1 :first upstream patchset: http://lists.gnu.org/archive/html/grub-devel/2016-02/msg00264.html Fu Wei (4): i386,xen: Add xen_hypervisor and xen_module aliases for i386 arm64: add "--nounzip" option support in xen_module command * util/grub.d/20_linux_xen.in: Add xen_boot command support arm64: update the introduction of xen boot commands in docs/grub.texi docs/grub.texi | 32 +++++++++----------------------- grub-core/loader/arm64/xen_boot.c | 17 +++++++++++++++++ grub-core/loader/i386/xen.c | 7 +++++++ grub-core/normal/main.c | 2 +- util/grub.d/20_linux_xen.in | 13 ++++++++++--- 5 files changed, 44 insertions(+), 27 deletions(-) -- 2.5.5

7 years, 5 months

[PATCH 1/3] Platforms/ARM/Juno: Fix IO window translate offset in PCIe root complex

by Sudeep Holla

XPress-RICH3 PCIe driver initialises the root complex with the same source and target address for IO window which makes translate offset 0. This patch fixes the translate offset for the IO window in Juno PCIe root complex ACPI table. Contributed-under: TianoCore Contribution Agreement 1.0 Cc: Ard Biesheuvel <ard.biesheuvel(a)linaro.org> Cc: Leif Lindholm <leif.lindholm(a)linaro.org> Signed-off-by: Sudeep Holla <sudeep.holla(a)arm.com> --- Platforms/ARM/Juno/AcpiTables/AcpiSsdtRootPci.asl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Platforms/ARM/Juno/AcpiTables/AcpiSsdtRootPci.asl b/Platforms/ARM/Juno/AcpiTables/AcpiSsdtRootPci.asl index 800d2cb3b2fb..ab5041db731a 100644 --- a/Platforms/ARM/Juno/AcpiTables/AcpiSsdtRootPci.asl +++ b/Platforms/ARM/Juno/AcpiTables/AcpiSsdtRootPci.asl @@ -109,7 +109,7 @@ DefinitionBlock("SsdtPci.aml", "SSDT", 1, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_OEM 0x00000000, // Granularity 0x5f800000, // Min Base Address 0x5fffffff, // Max Base Address - 0x5f800000, // Translate + 0x00000000, // Translate 0x00800000 // Length ) }) // Name(RBUF) -- 1.9.1

7 years, 6 months

[RFC/RFT PATCH] Drivers/Net/MarvellYukonDxe: remove redundant copy on RX path

by Ard Biesheuvel

The RX path in MarvellYukonDxe uses DMA buffers allocated via EFI_PCI_IO_PROTOCOL::AllocateBuffer(), and copies the contents of each into a temporary buffer, whose contents are copied yet another time before arriving at the caller of EFI_SIMPLE_NETWORK_PROTOCOL::Receive() This is inefficient for several reasons: - the streaming bus master DMA operations used for RX do not require the use of buffers allocated via EFI_PCI_IO_PROTOCOL::AllocateBuffer(), which may return uncached memory on platforms with non-coherent DMA - EFI_PCI_IO_PROTOCOL::AllocateBuffer() performs page based allocations, which means the UEFI memory map is modified for every packet received, now that the improper reuse of DMA buffers has been fixed. So drop the call to EFI_PCI_IO_PROTOCOL::AllocateBuffer(), and instead, perform a pool allocation whose ownership is transferred from the RX ring to the RX linked list, which removes the need for a copy. Also, since pool allocations decay to page based allocations for sizes that equal or exceed EFI_PAGE_SIZE, reduce MAX_SUPPORTED_PACKET_SIZE to the Ethernet default of 1500 bytes. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel(a)linaro.org> --- It builds, but does it run? I have no clue, since I don't own a Juno or a Softiron 1000. Comments and testing appreciated. Thanks. Drivers/Net/MarvellYukonDxe/if_msk.c | 26 ++++++-------------- Drivers/Net/MarvellYukonDxe/if_msk.h | 2 +- 2 files changed, 9 insertions(+), 19 deletions(-) diff --git a/Drivers/Net/MarvellYukonDxe/if_msk.c b/Drivers/Net/MarvellYukonDxe/if_msk.c index ecd716a66b55..d49c8e92a69a 100644 --- a/Drivers/Net/MarvellYukonDxe/if_msk.c +++ b/Drivers/Net/MarvellYukonDxe/if_msk.c @@ -595,7 +595,7 @@ msk_newbuf ( rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; - Status = mPciIo->AllocateBuffer (mPciIo, AllocateAnyPages, EfiBootServicesData, EFI_SIZE_TO_PAGES (Length), &Buffer, 0); + Status = gBS->AllocatePool (EfiBootServicesData, Length, &Buffer); if (EFI_ERROR (Status)) { return Status; } @@ -603,8 +603,7 @@ msk_newbuf ( Status = mPciIo->Map (mPciIo, EfiPciIoOperationBusMasterWrite, Buffer, &Length, &PhysAddr, &Mapping); if (EFI_ERROR (Status)) { - Length = MAX_SUPPORTED_PACKET_SIZE; - mPciIo->FreeBuffer (mPciIo, EFI_SIZE_TO_PAGES (Length), Buffer); + gBS->FreePool (Buffer); return Status; } @@ -1630,7 +1629,7 @@ msk_txrx_dma_free ( mPciIo->Unmap (mPciIo, rxd->rx_m.DmaMapping); // Free Rx buffers as we own these if(rxd->rx_m.Buf != NULL) { - mPciIo->FreeBuffer (mPciIo, EFI_SIZE_TO_PAGES (rxd->rx_m.Length), rxd->rx_m.Buf); + gBS->FreePool (rxd->rx_m.Buf); rxd->rx_m.Buf = NULL; } gBS->SetMem (&(rxd->rx_m), sizeof (MSK_DMA_BUF), 0); @@ -1933,23 +1932,14 @@ msk_rxeof ( if (!EFI_ERROR (Status)) { gBS->SetMem (m_link, sizeof (MSK_LINKED_SYSTEM_BUF), 0); m_link->Signature = RX_MBUF_SIGNATURE; - Status = gBS->AllocatePool (EfiBootServicesData, - len, - (VOID**) &m_link->SystemBuf.Buf); - if(!EFI_ERROR (Status)) { - gBS->CopyMem (m_link->SystemBuf.Buf, m.Buf, len); - m_link->SystemBuf.Length = len; - - InsertTailList (&mSoftc->ReceiveQueueHead, &m_link->Link); - } else { - DEBUG ((EFI_D_NET, "Marvell Yukon: failed to allocate DMA buffer. Dropping Frame\n")); - gBS->FreePool (m_link); - } + m_link->SystemBuf.Buf = m.Buf; + m_link->SystemBuf.Length = len; + + InsertTailList (&mSoftc->ReceiveQueueHead, &m_link->Link); } else { DEBUG ((EFI_D_NET, "Marvell Yukon: failed to allocate receive buffer link. Dropping Frame\n")); + gBS->FreePool (m.Buf); } - - mPciIo->FreeBuffer (mPciIo, EFI_SIZE_TO_PAGES (m.Length), m.Buf); } while (0); MSK_RX_INC (sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT); diff --git a/Drivers/Net/MarvellYukonDxe/if_msk.h b/Drivers/Net/MarvellYukonDxe/if_msk.h index a5025a39ecf3..66513d3c54c1 100644 --- a/Drivers/Net/MarvellYukonDxe/if_msk.h +++ b/Drivers/Net/MarvellYukonDxe/if_msk.h @@ -15,7 +15,7 @@ #include <Uefi.h> -#define MAX_SUPPORTED_PACKET_SIZE EFI_PAGE_SIZE +#define MAX_SUPPORTED_PACKET_SIZE (1500) EFI_STATUS mskc_probe (EFI_PCI_IO_PROTOCOL *PciIo); -- 2.7.4

7 years, 7 months

Questions about ARM SBSA v3.0 and SBBR v1.0

by Heyi Guo

Hi folks, I have some questions about ARM SBSA v3.0 and SBBR v1.0. Could anyone please provide the answers or some ideas? 1. In SBSA it says that I/O virtualization property should be expressed by system firmware data. Then how to express this information by ACPI? Is only IORT table related? Or is there any examples? 2. In SBSA Section 4.1.3, page 14 as below, does the term "memory" here also include peripheral memory mapped IO spaces? Does the term "access" include both "read" and "write"? If write is also included, I'm afraid there might be some critical configuration registers which will cause unpredicted behavior or even system hang due to unintended random write. 3. In SBBR, EFI_LOAD_FILE2_PROTOCOL is a required protocol. However,it is not used for boot in UEFI, and is mainly used for loading PCIe option ROM in EDK2 implementation. So why is this protocol required while PCIe is not mandatory for ARM server? 4. In SBBR, for IPv6 related protocols, it is said that they are optional on platforms that do not support networking. The question is, on platforms that *do* support networking, do IPv6 protocols become mandatory? Or is it allowed for only supporting IPv4 protocols? Thanks and regards. Heyi

7 years, 7 months

[PATCH 0/2] Cello: add firmware uploader for Renesas PD720202

by Ard Biesheuvel

This is a completely untested but complete implementation of a firmware uploader for the Renesas PD720202 PCIe XHCI controller. It is enabled for Cello in patch #2 if '-D RENESAS_XHCI_FW_DIR=<dir>' is passed on the build command line, where it expects to find the firmware image, in a file called K2013080.mem Ard Biesheuvel (2): Drivers/Xhci: implement firmware download driver for Renesas PD720202 Platforms/AMD/CelloBoard: add Renesas PD720202 firmware downloader Drivers/Xhci/RenesasFirmwarePD720202/RenesasFirmwarePD720202.c | 365 ++++++++++++++++++++ Drivers/Xhci/RenesasFirmwarePD720202/RenesasFirmwarePD720202.inf | 43 +++ OpenPlatformPkg.dec | 3 + Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc | 4 + Platforms/AMD/Styx/CelloBoard/CelloBoard.fdf | 10 + 5 files changed, 425 insertions(+) create mode 100644 Drivers/Xhci/RenesasFirmwarePD720202/RenesasFirmwarePD720202.c create mode 100644 Drivers/Xhci/RenesasFirmwarePD720202/RenesasFirmwarePD720202.inf -- 2.7.4

7 years, 7 months

[PATCH] Platforms/ARM/Juno: limit ACPI support to v5.0 and higher

by Sudeep Holla

The ACPI spec predates the AARCH64 architecture by 5 versions, so there is no point in supporting anything below v5.0. So set the PCD that controls the ACPI table generation to the appropriate value. Based on the commit e0692789058e ("ArmVirtPkg/ArmVirtQemu: limit ACPI support to v5.0 and higher") in the upstream TianoCore by Ard Biesheuvel Contributed-under: TianoCore Contribution Agreement 1.0 Cc: Ard Biesheuvel <ard.biesheuvel(a)linaro.org> Cc: Leif Lindholm <leif.lindholm(a)linaro.org> Cc: Evan Lloyd <Evan.Lloyd(a)arm.com> Signed-off-by: Sudeep Holla <sudeep.holla(a)arm.com> --- Platforms/ARM/Juno/ArmJuno.dsc | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Platforms/ARM/Juno/ArmJuno.dsc b/Platforms/ARM/Juno/ArmJuno.dsc index c51d8f2e21ab..3029999bc66f 100644 --- a/Platforms/ARM/Juno/ArmJuno.dsc +++ b/Platforms/ARM/Juno/ArmJuno.dsc @@ -183,6 +183,10 @@ # gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0300 gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosDocRev|0x0 + # + # ACPI Table Version + # + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20 [PcdsPatchableInModule] # Console Resolution (Full HD) -- 2.7.4

7 years, 7 months

[PATCH 0/7] Patches for the MarvellYukon driver

by Alan Ott

These patches are for v4 of the MarvellYukon driver posted by Daniil Egranov on June 16 to this mailing list. The impetus was to get this driver to work on a SoftIron Overdrive 1000 board using the AMD Opteron-A (Seattle/Styx) SoC. On this platform, in my testing, edk2 allocates DMA buffers with 64-bit addresses. The Marvell Yukon driver as posted did not support 64-bit addresses, and simply truncated any DMA address to 32-bits. After consulting with Ard Biesheuvel and Leif Lindholm on IRC, it seemed the proper fix was to add support for 64-bit DMA. For this I went back to the original source of this driver (FreeBSD), and brought over the appropriate code. A couple of patches are basic fixes, but the one titled "Don't re-use DMA buffers" changes how handling of DMA buffers works. This patch makes it work closer to how the FreeBSD implementation works and also adds some required DMA function calls. Its commit message is worth a read. I don't have a Juno board to test this on, so while this does work on my Overdrive 1000, there's a chance I broke something for other users. Let me know! Alan. Alan Ott (7): Drivers/Net/MarvellYukon: Remove ARM-specific include Drivers/Net/MarvellYukon: Set Dual Address Cycle Attribute Drivers/Net/MarvellYukon: Put model_name under MDEPKG_NDEBUG ifndef Drivers/Net/MarvellYukon: Use EFI_SIZE_TO_PAGES() Drivers/Net/MarvellYukon: Don't re-use DMA buffers Drivers/Net/MarvellYukon: Zero allocated memory for DMA receive buffers Drivers/Net/MarvellYukon: Add 64-bit DMA support Drivers/Net/MarvellYukonDxe/DeviceConfig.c | 4 +- Drivers/Net/MarvellYukonDxe/if_msk.c | 95 +++++++++++++++++++++++------- Drivers/Net/MarvellYukonDxe/if_mskreg.h | 17 +++++- 3 files changed, 91 insertions(+), 25 deletions(-) -- 2.5.0

7 years, 7 months

[PATCH] Platforms/Styx: ignore PcdArmPrimaryCoreMask

by Ard Biesheuvel

The PCD PcdArmPrimaryCoreMask is of dubious value, not only because it is unclear what the point is of masking out bits before comparing a given MPIDR_EL1 value with a known value belonging to the primary core, but also because the default value of 0xF03 masks out bits that belong to the actual affinity levels. For Styx, simply ignore the mask altogether. Since its version of ArmPlatformPeiBootAction () records the primary MPIDR_EL1 value upon first entry, we know its exact value, and no masking is necessary. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel(a)linaro.org> --- Hello Alan, Any chance you could try this patch, and check whether it solves the regression you have been experiencing? I'd try it myself it it weren't for the fact that my SPI flash programmer is broken atm. Thanks, Ard. Platforms/AMD/Styx/Library/AmdStyxLib/AArch64/Helper.S | 3 --- Platforms/AMD/Styx/Library/AmdStyxLib/AmdStyxLib.inf | 1 - Platforms/AMD/Styx/Library/AmdStyxLib/AmdStyxLibSec.inf | 1 - 3 files changed, 5 deletions(-) diff --git a/Platforms/AMD/Styx/Library/AmdStyxLib/AArch64/Helper.S b/Platforms/AMD/Styx/Library/AmdStyxLib/AArch64/Helper.S index a3ac60282706..b7ec02f0e69f 100644 --- a/Platforms/AMD/Styx/Library/AmdStyxLib/AArch64/Helper.S +++ b/Platforms/AMD/Styx/Library/AmdStyxLib/AArch64/Helper.S @@ -58,9 +58,6 @@ ASM_FUNC(ArmGetCpuCountPerCluster) // IN UINTN MpId // ); ASM_FUNC(ArmPlatformIsPrimaryCore) - MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCoreMask)) - and x0, x0, x1 - ldr w1, PrimaryCoreMpid cmp w0, w1 diff --git a/Platforms/AMD/Styx/Library/AmdStyxLib/AmdStyxLib.inf b/Platforms/AMD/Styx/Library/AmdStyxLib/AmdStyxLib.inf index 4a6469ee016c..8e9169161d16 100644 --- a/Platforms/AMD/Styx/Library/AmdStyxLib/AmdStyxLib.inf +++ b/Platforms/AMD/Styx/Library/AmdStyxLib/AmdStyxLib.inf @@ -67,7 +67,6 @@ gAmdStyxTokenSpaceGuid.PcdTrustedFWMemorySize [FixedPcd] - gArmTokenSpaceGuid.PcdArmPrimaryCoreMask gArmTokenSpaceGuid.PcdArmPrimaryCore gArmPlatformTokenSpaceGuid.PcdCoreCount diff --git a/Platforms/AMD/Styx/Library/AmdStyxLib/AmdStyxLibSec.inf b/Platforms/AMD/Styx/Library/AmdStyxLib/AmdStyxLibSec.inf index 0b9b6287168d..2a2d6ffb8c64 100644 --- a/Platforms/AMD/Styx/Library/AmdStyxLib/AmdStyxLibSec.inf +++ b/Platforms/AMD/Styx/Library/AmdStyxLib/AmdStyxLibSec.inf @@ -62,7 +62,6 @@ gArmTokenSpaceGuid.PcdFvBaseAddress [FixedPcd] - gArmTokenSpaceGuid.PcdArmPrimaryCoreMask gArmTokenSpaceGuid.PcdArmPrimaryCore gArmPlatformTokenSpaceGuid.PcdCoreCount -- 2.7.4

7 years, 7 months

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Linaro-uefi August 2016